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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id c185sm1462385wma.8.2021.10.19.00.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Oct 2021 00:11:04 -0700 (PDT) Date: Tue, 19 Oct 2021 09:11:03 +0200 From: Igor Mammedov To: Bin Meng Subject: Re: [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Message-ID: <20211019091103.68908df5@redhat.com> In-Reply-To: <20211018153829.24382-2-bmeng.cn@gmail.com> References: <20211018153829.24382-1-bmeng.cn@gmail.com> <20211018153829.24382-2-bmeng.cn@gmail.com> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 18 Oct 2021 23:38:25 +0800 Bin Meng wrote: > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing MachineClass::default_ram_id to > opt in to memdev scheme. > > Signed-off-by: Bin Meng > --- > > hw/riscv/opentitan.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 9803ae6d70..c356293d29 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -67,17 +67,14 @@ static void opentitan_board_init(MachineState *machine) > const MemMapEntry *memmap = ibex_memmap; > OpenTitanState *s = g_new0(OpenTitanState, 1); > MemoryRegion *sys_mem = get_system_memory(); > - MemoryRegion *main_mem = g_new(MemoryRegion, 1); It is likely that you are missing fixed size check here (looking at code it seems to me that board doesn't support variable RAM size) See commit 00b9829f83c for example. > /* Initialize SoC */ > object_initialize_child(OBJECT(machine), "soc", &s->soc, > TYPE_RISCV_IBEX_SOC); > qdev_realize(DEVICE(&s->soc), NULL, &error_abort); > > - memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", > - memmap[IBEX_DEV_RAM].size, &error_fatal); > memory_region_add_subregion(sys_mem, > - memmap[IBEX_DEV_RAM].base, main_mem); > + memmap[IBEX_DEV_RAM].base, machine->ram); > > if (machine->firmware) { > riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); > @@ -95,6 +92,7 @@ static void opentitan_machine_init(MachineClass *mc) > mc->init = opentitan_board_init; > mc->max_cpus = 1; > mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; > + mc->default_ram_id = "riscv.lowrisc.ibex.ram"; Are you missing "mc->default_ram_size = memmap[IBEX_DEV_RAM].size" here? otherwise it will default to generic: hw/core/machine.c: mc->default_ram_size = 128 * MiB; > } > > DEFINE_MACHINE("opentitan", opentitan_machine_init)