From: Igor Mammedov <imammedo@redhat.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: qemu-riscv@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
Date: Tue, 19 Oct 2021 09:16:22 +0200 [thread overview]
Message-ID: <20211019091622.1e606d94@redhat.com> (raw)
In-Reply-To: <20211018153829.24382-5-bmeng.cn@gmail.com>
On Mon, 18 Oct 2021 23:38:28 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
>
> hw/riscv/sifive_u.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index fc5790b8ce..0217006c27 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -528,7 +528,6 @@ static void sifive_u_machine_init(MachineState *machine)
> const MemMapEntry *memmap = sifive_u_memmap;
> SiFiveUState *s = RISCV_U_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> MemoryRegion *flash0 = g_new(MemoryRegion, 1);
> target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
> target_ulong firmware_end_addr, kernel_start_addr;
> @@ -549,10 +548,8 @@ static void sifive_u_machine_init(MachineState *machine)
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* register RAM */
> - memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
> - machine->ram_size, &error_fatal);
> memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
> - main_mem);
> + machine->ram);
>
> /* register QSPI0 Flash */
> memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
> @@ -748,6 +745,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
> mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
> mc->default_cpu_type = SIFIVE_U_CPU;
> mc->default_cpus = mc->min_cpus;
> + mc->default_ram_id = "riscv.sifive.u.ram";
>
> object_class_property_add_bool(oc, "start-in-flash",
> sifive_u_machine_get_start_in_flash,
next prev parent reply other threads:[~2021-10-19 7:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-18 15:38 [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-18 15:38 ` [PATCH 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-19 7:11 ` Igor Mammedov
2021-10-19 12:57 ` Bin Meng
2021-10-18 15:38 ` [PATCH 3/6] hw/riscv: shakti_c: " Bin Meng
2021-10-19 7:12 ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-19 7:15 ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 5/6] hw/riscv: sifive_u: " Bin Meng
2021-10-19 7:16 ` Igor Mammedov [this message]
2021-10-18 15:38 ` [PATCH 6/6] hw/riscv: spike: " Bin Meng
2021-10-19 7:17 ` Igor Mammedov
2021-10-18 15:51 ` [PATCH 1/6] hw/riscv: microchip_pfsoc: " Philippe Mathieu-Daudé
2021-10-18 16:00 ` Bin Meng
2021-10-19 7:39 ` Igor Mammedov
2021-10-20 1:55 ` Bin Meng
2021-10-20 8:32 ` Igor Mammedov
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