From: Michael Roth <michael.roth@amd.com>
To: <qemu-devel@nongnu.org>
Cc: <qemu-stable@nongnu.org>,
Gollu Appalanaidu <anaidu.gollu@samsung.com>,
Klaus Jensen <k.jensen@samsung.com>
Subject: [PATCH 39/64] hw/block/nvme: align with existing style
Date: Tue, 19 Oct 2021 09:09:19 -0500 [thread overview]
Message-ID: <20211019140944.152419-40-michael.roth@amd.com> (raw)
In-Reply-To: <20211019140944.152419-1-michael.roth@amd.com>
From: Gollu Appalanaidu <anaidu.gollu@samsung.com>
While QEMU coding style prefers lowercase hexadecimals in constants, the
NVMe subsystem uses the format from the NVMe specifications in comments,
i.e. 'h' suffix instead of '0x' prefix.
Fix this up across the code base.
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
[k.jensen: updated message; added conversion in a couple of missing comments]
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
(cherry picked from commit 312c3531bba416e589f106db8c8241fc6e7e6332)
*context dependency for 2b02aabc9d
Signed-off-by: Michael Roth <michael.roth@amd.com>
---
hw/block/nvme-ns.c | 2 +-
hw/block/nvme.c | 67 +++++++++++++++++++++++++-------------------
include/block/nvme.h | 10 +++----
3 files changed, 44 insertions(+), 35 deletions(-)
diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c
index 7bb618f182..a0895614d9 100644
--- a/hw/block/nvme-ns.c
+++ b/hw/block/nvme-ns.c
@@ -303,7 +303,7 @@ static void nvme_ns_init_zoned(NvmeNamespace *ns)
id_ns_z = g_malloc0(sizeof(NvmeIdNsZoned));
- /* MAR/MOR are zeroes-based, 0xffffffff means no limit */
+ /* MAR/MOR are zeroes-based, FFFFFFFFFh means no limit */
id_ns_z->mar = cpu_to_le32(ns->params.max_active_zones - 1);
id_ns_z->mor = cpu_to_le32(ns->params.max_open_zones - 1);
id_ns_z->zoc = 0;
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 5fe082ec34..2c7ca587c5 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -12,10 +12,19 @@
* Reference Specs: http://www.nvmexpress.org, 1.4, 1.3, 1.2, 1.1, 1.0e
*
* https://nvmexpress.org/developers/nvme-specification/
- */
-
-/**
- * Usage: add options:
+ *
+ *
+ * Notes on coding style
+ * ---------------------
+ * While QEMU coding style prefers lowercase hexadecimals in constants, the
+ * NVMe subsystem use thes format from the NVMe specifications in the comments
+ * (i.e. 'h' suffix instead of '0x' prefix).
+ *
+ * Usage
+ * -----
+ * See docs/system/nvme.rst for extensive documentation.
+ *
+ * Add options:
* -drive file=<file>,if=none,id=<drive_id>
* -device nvme-subsys,id=<subsys_id>,nqn=<nqn_id>
* -device nvme,serial=<serial>,id=<bus_name>, \
@@ -3607,18 +3616,18 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
/*
* In the base NVM command set, Flush may apply to all namespaces
- * (indicated by NSID being set to 0xFFFFFFFF). But if that feature is used
+ * (indicated by NSID being set to FFFFFFFFh). But if that feature is used
* along with TP 4056 (Namespace Types), it may be pretty screwed up.
*
- * If NSID is indeed set to 0xFFFFFFFF, we simply cannot associate the
+ * If NSID is indeed set to FFFFFFFFh, we simply cannot associate the
* opcode with a specific command since we cannot determine a unique I/O
- * command set. Opcode 0x0 could have any other meaning than something
+ * command set. Opcode 0h could have any other meaning than something
* equivalent to flushing and say it DOES have completely different
- * semantics in some other command set - does an NSID of 0xFFFFFFFF then
+ * semantics in some other command set - does an NSID of FFFFFFFFh then
* mean "for all namespaces, apply whatever command set specific command
- * that uses the 0x0 opcode?" Or does it mean "for all namespaces, apply
- * whatever command that uses the 0x0 opcode if, and only if, it allows
- * NSID to be 0xFFFFFFFF"?
+ * that uses the 0h opcode?" Or does it mean "for all namespaces, apply
+ * whatever command that uses the 0h opcode if, and only if, it allows NSID
+ * to be FFFFFFFFh"?
*
* Anyway (and luckily), for now, we do not care about this since the
* device only supports namespace types that includes the NVM Flush command
@@ -3934,7 +3943,7 @@ static uint16_t nvme_changed_nslist(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
NVME_CHANGED_NSID_SIZE) {
/*
* If more than 1024 namespaces, the first entry in the log page should
- * be set to 0xffffffff and the others to 0 as spec.
+ * be set to FFFFFFFFh and the others to 0 as spec.
*/
if (i == ARRAY_SIZE(nslist)) {
memset(nslist, 0x0, sizeof(nslist));
@@ -4332,7 +4341,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req,
trace_pci_nvme_identify_nslist(min_nsid);
/*
- * Both 0xffffffff (NVME_NSID_BROADCAST) and 0xfffffffe are invalid values
+ * Both FFFFFFFFh (NVME_NSID_BROADCAST) and FFFFFFFFEh are invalid values
* since the Active Namespace ID List should return namespaces with ids
* *higher* than the NSID specified in the command. This is also specified
* in the spec (NVM Express v1.3d, Section 5.15.4).
@@ -4379,7 +4388,7 @@ static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req,
trace_pci_nvme_identify_nslist_csi(min_nsid, c->csi);
/*
- * Same as in nvme_identify_nslist(), 0xffffffff/0xfffffffe are invalid.
+ * Same as in nvme_identify_nslist(), FFFFFFFFh/FFFFFFFFEh are invalid.
*/
if (min_nsid >= NVME_NSID_BROADCAST - 1) {
return NVME_INVALID_NSID | NVME_DNR;
@@ -4446,7 +4455,7 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
/*
* Because the NGUID and EUI64 fields are 0 in the Identify Namespace data
- * structure, a Namespace UUID (nidt = 0x3) must be reported in the
+ * structure, a Namespace UUID (nidt = 3h) must be reported in the
* Namespace Identification Descriptor. Add the namespace UUID here.
*/
ns_descrs->uuid.hdr.nidt = NVME_NIDT_UUID;
@@ -4595,7 +4604,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
/*
* The Reservation Notification Mask and Reservation Persistence
* features require a status code of Invalid Field in Command when
- * NSID is 0xFFFFFFFF. Since the device does not support those
+ * NSID is FFFFFFFFh. Since the device does not support those
* features we can always return Invalid Namespace or Format as we
* should do for all other features.
*/
@@ -4847,15 +4856,15 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
}
/*
- * NVMe v1.3, Section 5.21.1.7: 0xffff is not an allowed value for NCQR
+ * NVMe v1.3, Section 5.21.1.7: FFFFh is not an allowed value for NCQR
* and NSQR.
*/
if ((dw11 & 0xffff) == 0xffff || ((dw11 >> 16) & 0xffff) == 0xffff) {
return NVME_INVALID_FIELD | NVME_DNR;
}
- trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
- ((dw11 >> 16) & 0xFFFF) + 1,
+ trace_pci_nvme_setfeat_numq((dw11 & 0xffff) + 1,
+ ((dw11 >> 16) & 0xffff) + 1,
n->params.max_ioqpairs,
n->params.max_ioqpairs);
req->cqe.result = cpu_to_le32((n->params.max_ioqpairs - 1) |
@@ -5493,7 +5502,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
n->bar.cc = data;
}
break;
- case 0x1C: /* CSTS */
+ case 0x1c: /* CSTS */
if (data & (1 << 4)) {
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported,
"attempted to W1C CSTS.NSSRO"
@@ -5505,7 +5514,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
}
break;
case 0x20: /* NSSR */
- if (data == 0x4E564D65) {
+ if (data == 0x4e564d65) {
trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
} else {
/* The spec says that writes of other values have no effect */
@@ -5575,11 +5584,11 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
n->bar.cmbmsc = (n->bar.cmbmsc & 0xffffffff) | (data << 32);
return;
- case 0xE00: /* PMRCAP */
+ case 0xe00: /* PMRCAP */
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly,
"invalid write to PMRCAP register, ignored");
return;
- case 0xE04: /* PMRCTL */
+ case 0xe04: /* PMRCTL */
n->bar.pmrctl = data;
if (NVME_PMRCTL_EN(data)) {
memory_region_set_enabled(&n->pmr.dev->mr, true);
@@ -5590,19 +5599,19 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
n->pmr.cmse = false;
}
return;
- case 0xE08: /* PMRSTS */
+ case 0xe08: /* PMRSTS */
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly,
"invalid write to PMRSTS register, ignored");
return;
- case 0xE0C: /* PMREBS */
+ case 0xe0C: /* PMREBS */
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly,
"invalid write to PMREBS register, ignored");
return;
- case 0xE10: /* PMRSWTP */
+ case 0xe10: /* PMRSWTP */
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
"invalid write to PMRSWTP register, ignored");
return;
- case 0xE14: /* PMRMSCL */
+ case 0xe14: /* PMRMSCL */
if (!NVME_CAP_PMRS(n->bar.cap)) {
return;
}
@@ -5622,7 +5631,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
}
return;
- case 0xE18: /* PMRMSCU */
+ case 0xe18: /* PMRMSCU */
if (!NVME_CAP_PMRS(n->bar.cap)) {
return;
}
@@ -5664,7 +5673,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
* from PMRSTS should ensure prior writes
* made it to persistent media
*/
- if (addr == 0xE08 &&
+ if (addr == 0xe08 &&
(NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size);
}
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 4ac926fbc6..0739e0d665 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -848,8 +848,8 @@ enum NvmeStatusCodes {
NVME_FW_REQ_SUSYSTEM_RESET = 0x0110,
NVME_NS_ALREADY_ATTACHED = 0x0118,
NVME_NS_PRIVATE = 0x0119,
- NVME_NS_NOT_ATTACHED = 0x011A,
- NVME_NS_CTRL_LIST_INVALID = 0x011C,
+ NVME_NS_NOT_ATTACHED = 0x011a,
+ NVME_NS_CTRL_LIST_INVALID = 0x011c,
NVME_CONFLICTING_ATTRS = 0x0180,
NVME_INVALID_PROT_INFO = 0x0181,
NVME_WRITE_TO_RO = 0x0182,
@@ -1409,9 +1409,9 @@ typedef enum NvmeZoneState {
NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02,
NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03,
NVME_ZONE_STATE_CLOSED = 0x04,
- NVME_ZONE_STATE_READ_ONLY = 0x0D,
- NVME_ZONE_STATE_FULL = 0x0E,
- NVME_ZONE_STATE_OFFLINE = 0x0F,
+ NVME_ZONE_STATE_READ_ONLY = 0x0d,
+ NVME_ZONE_STATE_FULL = 0x0e,
+ NVME_ZONE_STATE_OFFLINE = 0x0f,
} NvmeZoneState;
static inline void _nvme_check_size(void)
--
2.25.1
next prev parent reply other threads:[~2021-10-19 14:58 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 14:08 [PATCH 00/64] Patch Round-up for stable 6.0.1, freeze on 2021-10-26 Michael Roth
2021-10-19 14:08 ` [PATCH 01/64] multi-process: Initialize variables declared with g_auto* Michael Roth
2021-10-19 14:08 ` [PATCH 02/64] linux-user/aarch64: Enable hwcap for RND, BTI, and MTE Michael Roth
2021-10-19 14:08 ` [PATCH 03/64] docs/system: Document the removal of "compat" property for POWER CPUs Michael Roth
2021-10-19 14:08 ` [PATCH 04/64] monitor/qmp: fix race on CHR_EVENT_CLOSED without OOB Michael Roth
2021-10-19 14:08 ` [PATCH 05/64] migration/rdma: Fix cm_event used before being initialized Michael Roth
2021-10-19 14:08 ` [PATCH 06/64] target/i386: Exit tb after wrmsr Michael Roth
2021-10-19 14:08 ` [PATCH 07/64] target/ppc: Fix load endianness for lxvwsx/lxvdsx Michael Roth
2021-10-19 14:08 ` [PATCH 08/64] vl: allow not specifying size in -m when using -M memory-backend Michael Roth
2021-10-19 14:08 ` [PATCH 09/64] target/xtensa: fix access ring in l32ex Michael Roth
2021-10-19 14:08 ` [PATCH 10/64] qemu-option: support accept-any QemuOptsList in qemu_opts_absorb_qdict Michael Roth
2021-10-19 14:08 ` [PATCH 11/64] qemu-config: load modules when instantiating option groups Michael Roth
2021-10-19 14:08 ` [PATCH 12/64] qemu-config: parse configuration files to a QDict Michael Roth
2021-10-19 14:08 ` [PATCH 13/64] vl: plumb keyval-based options into -readconfig Michael Roth
2021-10-19 14:08 ` [PATCH 14/64] vl: plug -object back " Michael Roth
2021-10-19 14:08 ` [PATCH 15/64] sockets: update SOCKET_ADDRESS_TYPE_FD listen(2) backlog Michael Roth
2021-10-19 14:08 ` [PATCH 16/64] hmp: Fix loadvm to resume the VM on success instead of failure Michael Roth
2021-10-19 14:08 ` [PATCH 17/64] configure: fix detection of gdbus-codegen Michael Roth
2021-10-19 14:08 ` [PATCH 18/64] vhost-vdpa: don't initialize backend_features Michael Roth
2021-10-19 14:08 ` [PATCH 19/64] esp: only assert INTR_DC interrupt flag if selection fails Michael Roth
2021-10-19 14:09 ` [PATCH 20/64] esp: only set ESP_RSEQ at the start of the select sequence Michael Roth
2021-10-19 14:09 ` [PATCH 21/64] runstate: Initialize Error * to NULL Michael Roth
2021-10-19 14:09 ` [PATCH 22/64] vfio: Fix unregister SaveVMHandler in vfio_migration_finalize Michael Roth
2021-10-19 14:09 ` [PATCH 23/64] vl: Fix an assert failure in error path Michael Roth
2021-10-19 14:09 ` [PATCH 24/64] tcg/sparc: Fix temp_allocate_frame vs sparc stack bias Michael Roth
2021-10-19 14:09 ` [PATCH 25/64] tcg: Allocate sufficient storage in temp_allocate_frame Michael Roth
2021-10-19 14:09 ` [PATCH 26/64] hw/pci-host/q35: Ignore write of reserved PCIEXBAR LENGTH field Michael Roth
2021-10-19 14:09 ` [PATCH 27/64] block/nvme: Fix VFIO_MAP_DMA failed: No space left on device Michael Roth
2021-10-19 14:09 ` [PATCH 28/64] crypto/tlscreds: Introduce qcrypto_tls_creds_check_endpoint() helper Michael Roth
2021-10-19 14:09 ` [PATCH 29/64] block/nbd: Use qcrypto_tls_creds_check_endpoint() Michael Roth
2021-10-19 14:09 ` [PATCH 30/64] qemu-nbd: " Michael Roth
2021-10-19 14:09 ` [PATCH 31/64] chardev/socket: " Michael Roth
2021-10-19 14:09 ` [PATCH 32/64] migration/tls: " Michael Roth
2021-10-19 14:09 ` [PATCH 33/64] ui/vnc: " Michael Roth
2021-10-19 14:09 ` [PATCH 34/64] crypto: Make QCryptoTLSCreds* structures private Michael Roth
2021-10-19 14:09 ` [PATCH 35/64] yank: Unregister function when using TLS migration Michael Roth
2021-10-19 14:09 ` [PATCH 36/64] tests: acpi: prepare for changing DSDT tables Michael Roth
2021-10-19 14:09 ` [PATCH 37/64] acpi: pc: revert back to v5.2 PCI slot enumeration Michael Roth
2021-10-19 14:09 ` [PATCH 38/64] tests: acpi: pc: update expected DSDT blobs Michael Roth
2021-10-19 14:09 ` Michael Roth [this message]
2021-10-19 14:09 ` [PATCH 40/64] hw/nvme: fix missing check for PMR capability Michael Roth
2021-10-19 14:09 ` [PATCH 41/64] hw/nvme: fix pin-based interrupt behavior (again) Michael Roth
2021-10-19 14:09 ` [PATCH 42/64] virtio-balloon: don't start free page hinting if postcopy is possible Michael Roth
2021-10-19 14:09 ` [PATCH 43/64] hw/net/can: sja1000 fix buff2frame_bas and buff2frame_pel when dlc is out of std CAN 8 bytes Michael Roth
2021-10-19 14:09 ` [PATCH 44/64] hw/sd/sdcard: Document out-of-range addresses for SEND_WRITE_PROT Michael Roth
2021-10-19 14:09 ` [PATCH 45/64] hw/sd/sdcard: Fix assertion accessing out-of-range addresses with CMD30 Michael Roth
2021-10-19 14:09 ` [PATCH 46/64] audio: Never send migration section Michael Roth
2021-10-19 14:09 ` [PATCH 47/64] target/arm: Don't skip M-profile reset entirely in user mode Michael Roth
2021-10-19 14:09 ` [PATCH 48/64] virtio-net: fix use after unmap/free for sg Michael Roth
2021-10-19 14:09 ` [PATCH 49/64] qemu-nbd: Change default cache mode to writeback Michael Roth
2021-10-19 14:09 ` [PATCH 50/64] hmp: Unbreak "change vnc" Michael Roth
2021-10-19 14:09 ` [PATCH 51/64] virtio-mem-pci: Fix memory leak when creating MEMORY_DEVICE_SIZE_CHANGE event Michael Roth
2021-10-19 14:09 ` [PATCH 52/64] uas: add stream number sanity checks Michael Roth
2021-10-19 14:09 ` [PATCH 53/64] usb/redir: avoid dynamic stack allocation (CVE-2021-3527) Michael Roth
2021-10-19 14:09 ` [PATCH 54/64] usb: limit combined packets to 1 MiB (CVE-2021-3527) Michael Roth
2021-10-19 14:09 ` [PATCH 55/64] vhost-user-gpu: fix memory disclosure in virgl_cmd_get_capset_info (CVE-2021-3545) Michael Roth
2021-10-19 14:09 ` [PATCH 56/64] vhost-user-gpu: fix resource leak in 'vg_resource_create_2d' (CVE-2021-3544) Michael Roth
2021-10-19 14:09 ` [PATCH 57/64] vhost-user-gpu: fix memory leak in vg_resource_attach_backing (CVE-2021-3544) Michael Roth
2021-10-19 14:09 ` [PATCH 58/64] vhost-user-gpu: fix memory leak while calling 'vg_resource_unref' (CVE-2021-3544) Michael Roth
2021-10-19 14:09 ` [PATCH 59/64] vhost-user-gpu: fix memory leak in 'virgl_cmd_resource_unref' (CVE-2021-3544) Michael Roth
2021-10-19 14:09 ` [PATCH 60/64] vhost-user-gpu: fix memory leak in 'virgl_resource_attach_backing' (CVE-2021-3544) Michael Roth
2021-10-19 14:09 ` [PATCH 61/64] vhost-user-gpu: fix OOB write in 'virgl_cmd_get_capset' (CVE-2021-3546) Michael Roth
2021-10-19 14:09 ` [PATCH 62/64] hw/rdma: Fix possible mremap overflow in the pvrdma device (CVE-2021-3582) Michael Roth
2021-10-19 14:09 ` [PATCH 63/64] pvrdma: Ensure correct input on ring init (CVE-2021-3607) Michael Roth
2021-10-19 14:09 ` [PATCH 64/64] pvrdma: Fix the ring init error flow (CVE-2021-3608) Michael Roth
2021-10-19 14:43 ` [PATCH 00/64] Patch Round-up for stable 6.0.1, freeze on 2021-10-26 Ani Sinha
2021-10-19 14:45 ` Michael S. Tsirkin
2021-10-19 18:22 ` Michael Roth
2021-10-19 23:05 ` Ani Sinha
2021-10-19 14:52 ` Christian Schoenebeck
2021-10-19 15:26 ` Greg Kurz
2021-10-19 15:37 ` Christian Schoenebeck
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