qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v5 00/16] target/riscv: Rationalize XLEN and operand length
@ 2021-10-19 15:24 Richard Henderson
  2021-10-19 15:24 ` [PATCH v5 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
                   ` (15 more replies)
  0 siblings, 16 replies; 21+ messages in thread
From: Richard Henderson @ 2021-10-19 15:24 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair.francis, qemu-riscv, zhiwei_liu

This is a partial patch set attempting to set things in the
right direction for both the UXL and RV128 patch sets.


r~


Changes for v5:
  * Fix cpu_dump, which asserted for -accel qtest.
    Instead of filtering CSRs explicitly in cpu_dump,
    let the riscv_csr_operations predicate do the job.
    This means we won't dump S-mode registers when RVS
    is not enabled, much like we currently filter on RVH.

Changes for v4:
  * Use riscv_csrrw_debug for cpu_dump.
    This fixes the issue that Alistair pointed out wrt the
    MSTATUS.SD bit not being correct in the dump; note that
    gdbstub already uses riscv_csrrw_debug, and so did not
    have a problem.
  * Align the registers in cpu_dump.

Changes for v3:
  * Fix CONFIG_ typo.
  * Fix ctzw typo.
  * Mark get_xlen unused (clang werror)
  * Compute MSTATUS_SD on demand.

Changes for v2:
  * Set mxl/sxl/uxl at reset.
  * Set sxl/uxl in write_mstatus.



Richard Henderson (16):
  target/riscv: Move cpu_get_tb_cpu_state out of line
  target/riscv: Create RISCVMXL enumeration
  target/riscv: Split misa.mxl and misa.ext
  target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
  target/riscv: Add MXL/SXL/UXL to TB_FLAGS
  target/riscv: Use REQUIRE_64BIT in amo_check64
  target/riscv: Properly check SEW in amo_op
  target/riscv: Replace is_32bit with get_xl/get_xlen
  target/riscv: Replace DisasContext.w with DisasContext.ol
  target/riscv: Use gen_arith_per_ol for RVM
  target/riscv: Adjust trans_rev8_32 for riscv64
  target/riscv: Use gen_unary_per_ol for RVB
  target/riscv: Use gen_shift*_per_ol for RVB, RVI
  target/riscv: Align gprs and fprs in cpu_dump
  target/riscv: Use riscv_csrrw_debug for cpu_dump
  target/riscv: Compute mstatus.sd on demand

 target/riscv/cpu.h                      |  73 +++------
 target/riscv/cpu_bits.h                 |   8 +-
 hw/riscv/boot.c                         |   2 +-
 linux-user/elfload.c                    |   2 +-
 linux-user/riscv/cpu_loop.c             |   2 +-
 semihosting/arm-compat-semi.c           |   2 +-
 target/riscv/cpu.c                      | 203 ++++++++++++++----------
 target/riscv/cpu_helper.c               |  92 ++++++++++-
 target/riscv/csr.c                      | 104 +++++++-----
 target/riscv/gdbstub.c                  |  10 +-
 target/riscv/machine.c                  |  10 +-
 target/riscv/monitor.c                  |   4 +-
 target/riscv/translate.c                | 174 +++++++++++++++-----
 target/riscv/insn_trans/trans_rvb.c.inc | 140 ++++++++--------
 target/riscv/insn_trans/trans_rvi.c.inc |  44 ++---
 target/riscv/insn_trans/trans_rvm.c.inc |  36 ++++-
 target/riscv/insn_trans/trans_rvv.c.inc |  29 ++--
 17 files changed, 581 insertions(+), 354 deletions(-)

-- 
2.25.1



^ permalink raw reply	[flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-10-19 23:12 UTC | newest]

Thread overview: 21+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-10-19 15:24 [PATCH v5 00/16] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-19 15:24 ` [PATCH v5 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-19 15:24 ` [PATCH v5 02/16] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-19 15:24 ` [PATCH v5 03/16] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-19 15:24 ` [PATCH v5 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-19 15:24 ` [PATCH v5 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-19 15:24 ` [PATCH v5 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-19 15:24 ` [PATCH v5 07/16] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-19 15:24 ` [PATCH v5 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-19 15:24 ` [PATCH v5 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-19 15:24 ` [PATCH v5 10/16] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-19 15:24 ` [PATCH v5 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-19 15:24 ` [PATCH v5 12/16] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-19 15:24 ` [PATCH v5 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-19 15:24 ` [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump Richard Henderson
2021-10-19 22:10   ` Alistair Francis
2021-10-19 23:10     ` Richard Henderson
2021-10-19 15:24 ` [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-19 22:12   ` Alistair Francis
2021-10-19 15:24 ` [PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-19 22:12   ` Alistair Francis

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).