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From: Igor Mammedov <imammedo@redhat.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: qemu-riscv@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
Date: Thu, 21 Oct 2021 10:48:17 +0200	[thread overview]
Message-ID: <20211021104817.7db6a276@redhat.com> (raw)
In-Reply-To: <20211020014112.7336-2-bmeng.cn@gmail.com>

On Wed, 20 Oct 2021 09:41:07 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:

> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
> 
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

> 
> ---
> 
> Changes in v2:
> - split RAM into low and high regions using aliases to machine->ram
> - rename mc->default_ram_id to "microchip.icicle.kit.ram"
> 
>  hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
>  1 file changed, 20 insertions(+), 16 deletions(-)
> 
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e475b6d511..3fc8545562 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -463,7 +463,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>      MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
>      MemoryRegion *mem_high = g_new(MemoryRegion, 1);
>      MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
> -    uint64_t mem_high_size;
> +    uint64_t mem_low_size, mem_high_size;
>      hwaddr firmware_load_addr;
>      const char *firmware_name;
>      bool kernel_as_payload = false;
> @@ -485,31 +485,34 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>                              TYPE_MICROCHIP_PFSOC);
>      qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>  
> +    /* Split RAM into low and high regions using aliases to machine->ram */
> +    mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
> +    mem_high_size = machine->ram_size - mem_low_size;
> +    memory_region_init_alias(mem_low, NULL,
> +                             "microchip.icicle.kit.ram_low", machine->ram,
> +                             0, mem_low_size);
> +    memory_region_init_alias(mem_high, NULL,
> +                             "microchip.icicle.kit.ram_high", machine->ram,
> +                             mem_low_size, mem_high_size);
> +
>      /* Register RAM */
> -    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
> -                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> -                           &error_fatal);
> -    memory_region_init_alias(mem_low_alias, NULL,
> -                             "microchip.icicle.kit.ram_low.alias",
> -                             mem_low, 0,
> -                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
>      memory_region_add_subregion(system_memory,
>                                  memmap[MICROCHIP_PFSOC_DRAM_LO].base,
>                                  mem_low);
> +    memory_region_add_subregion(system_memory,
> +                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> +                                mem_high);
> +
> +    /* Create aliases for the low and high RAM regions */
> +    memory_region_init_alias(mem_low_alias, NULL,
> +                             "microchip.icicle.kit.ram_low.alias",
> +                             mem_low, 0, mem_low_size);
>      memory_region_add_subregion(system_memory,
>                                  memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
>                                  mem_low_alias);
> -
> -    mem_high_size = machine->ram_size - 1 * GiB;
> -
> -    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
> -                           mem_high_size, &error_fatal);
>      memory_region_init_alias(mem_high_alias, NULL,
>                               "microchip.icicle.kit.ram_high.alias",
>                               mem_high, 0, mem_high_size);
> -    memory_region_add_subregion(system_memory,
> -                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> -                                mem_high);
>      memory_region_add_subregion(system_memory,
>                                  memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
>                                  mem_high_alias);
> @@ -606,6 +609,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
>                     MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
>      mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
>      mc->default_cpus = mc->min_cpus;
> +    mc->default_ram_id = "microchip.icicle.kit.ram";
>  
>      /*
>       * Map 513 MiB high memory, the mimimum required high memory size, because



  parent reply	other threads:[~2021-10-21  8:49 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-20  1:41 [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Bin Meng
2021-10-20  1:41 ` [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-20 23:06   ` Alistair Francis
2021-10-21  8:48   ` Igor Mammedov [this message]
2021-10-20  1:41 ` [PATCH v2 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-20 13:01   ` Philippe Mathieu-Daudé
2021-10-20 23:10   ` Alistair Francis
2021-10-21  8:44   ` Igor Mammedov
2021-10-20  1:41 ` [PATCH v2 3/6] hw/riscv: shakti_c: " Bin Meng
2021-10-20 23:11   ` Alistair Francis
2021-10-20  1:41 ` [PATCH v2 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-20 13:02   ` Philippe Mathieu-Daudé
2021-10-20 23:12   ` Alistair Francis
2021-10-21  8:43   ` Igor Mammedov
2021-10-20  1:41 ` [PATCH v2 5/6] hw/riscv: sifive_u: " Bin Meng
2021-10-20 23:12   ` Alistair Francis
2021-10-20  1:41 ` [PATCH v2 6/6] hw/riscv: spike: " Bin Meng
2021-10-20 23:13   ` Alistair Francis
2021-10-21 21:58 ` [PATCH v2 0/6] hw/riscv: Use MachineState::ram and MachineClass::default_ram_id in all machines Alistair Francis

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