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From: Corey Minyard <minyard@acm.org>
To: Hao Wu <wuhaotsh@google.com>
Cc: peter.maydell@linaro.org, Titus Rwantare <titusr@google.com>,
	venture@google.com, qemu-devel@nongnu.org,
	hskinnemoen@google.com, kfting@nuvoton.com, qemu-arm@nongnu.org,
	Avi.Fishman@nuvoton.com
Subject: Re: [PATCH v2 2/7] hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus
Date: Thu, 21 Oct 2021 13:50:17 -0500	[thread overview]
Message-ID: <20211021185017.GA66936@minyard.net> (raw)
In-Reply-To: <20211021183956.920822-3-wuhaotsh@google.com>

On Thu, Oct 21, 2021 at 11:39:51AM -0700, Hao Wu wrote:
> Originally we read in from SMBus when RXF_STS is cleared. However,
> the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
> module to read incorrect amount of bytes in FIFO mode when the number
> of bytes read changed. This patch fixes this issue.
> 
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> Reviewed-by: Titus Rwantare <titusr@google.com>

This looks ok.  I assume you can take this in with the rest of the
patches.

Acked-by: Corey Minyard <cminyard@mvista.com>

> ---
>  hw/i2c/npcm7xx_smbus.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c
> index f18e311556..1435daea94 100644
> --- a/hw/i2c/npcm7xx_smbus.c
> +++ b/hw/i2c/npcm7xx_smbus.c
> @@ -637,9 +637,6 @@ static void npcm7xx_smbus_write_rxf_sts(NPCM7xxSMBusState *s, uint8_t value)
>  {
>      if (value & NPCM7XX_SMBRXF_STS_RX_THST) {
>          s->rxf_sts &= ~NPCM7XX_SMBRXF_STS_RX_THST;
> -        if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) {
> -            npcm7xx_smbus_recv_fifo(s);
> -        }
>      }
>  }
>  
> @@ -651,6 +648,9 @@ static void npcm7xx_smbus_write_rxf_ctl(NPCM7xxSMBusState *s, uint8_t value)
>          new_ctl = KEEP_OLD_BIT(s->rxf_ctl, new_ctl, NPCM7XX_SMBRXF_CTL_LAST);
>      }
>      s->rxf_ctl = new_ctl;
> +    if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) {
> +        npcm7xx_smbus_recv_fifo(s);
> +    }
>  }
>  
>  static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size)
> -- 
> 2.33.0.1079.g6e70778dc9-goog
> 
> 


  reply	other threads:[~2021-10-21 18:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 18:39 [PATCH v2 0/7] Misc NPCM7XX patches Hao Wu
2021-10-21 18:39 ` [PATCH v2 1/7] hw/i2c: Clear ACK bit in NPCM7xx SMBus module Hao Wu
2021-11-01 17:35   ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 2/7] hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus Hao Wu
2021-10-21 18:50   ` Corey Minyard [this message]
2021-10-21 18:39 ` [PATCH v2 3/7] hw/adc: Fix CONV bit in NPCM7XX ADC CON register Hao Wu
2021-11-01 17:35   ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 4/7] hw/adc: Make adci[*] R/W in NPCM7XX ADC Hao Wu
2021-11-01 17:37   ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 5/7] hw/nvram: Update at24c EEPROM init function in NPCM7xx boards Hao Wu
2021-11-01 17:41   ` Peter Maydell
2021-11-01 17:47     ` Hao Wu
2021-11-03  9:13       ` Thomas Huth
2021-11-03 21:52         ` Hao Wu
2021-11-04 20:50           ` Peter Maydell
2021-10-21 18:39 ` [PATCH v2 6/7] hw/arm: quanta-gbs-bmc add i2c devices Hao Wu
2021-10-21 18:39 ` [PATCH v2 7/7] hw/arm: Add ID for NPCM7XX SMBus Hao Wu
2021-11-01 17:33   ` Peter Maydell
2021-11-01 22:54     ` Hao Wu
2021-11-02  8:55     ` Philippe Mathieu-Daudé
2021-11-03 10:16       ` Markus Armbruster

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