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Fri, 22 Oct 2021 06:40:35 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.39]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HbQTX28MNz1RtVl; Fri, 22 Oct 2021 06:40:31 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , Bin Meng Subject: [PULL 23/33] hw/riscv: opentitan: Update to the latest build Date: Fri, 22 Oct 2021 23:38:02 +1000 Message-Id: <20211022133812.3972903-24-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211022133812.3972903-1-alistair.francis@opensource.wdc.com> References: <20211022133812.3972903-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=9222bbd82=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alist= air.francis@wdc.com --- include/hw/riscv/opentitan.h | 6 +++--- hw/riscv/opentitan.c | 22 +++++++++++++++++----- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 9f93bebdac..eac35ef590 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -20,7 +20,7 @@ #define HW_OPENTITAN_H =20 #include "hw/riscv/riscv_hart.h" -#include "hw/intc/ibex_plic.h" +#include "hw/intc/sifive_plic.h" #include "hw/char/ibex_uart.h" #include "hw/timer/ibex_timer.h" #include "qom/object.h" @@ -34,7 +34,7 @@ struct LowRISCIbexSoCState { =20 /*< public >*/ RISCVHartArrayState cpus; - IbexPlicState plic; + SiFivePLICState plic; IbexUartState uart; IbexTimerState timer; =20 @@ -87,7 +87,7 @@ enum { }; =20 enum { - IBEX_TIMER_TIMEREXPIRED0_0 =3D 125, + IBEX_TIMER_TIMEREXPIRED0_0 =3D 126, IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 9803ae6d70..601f8deebe 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -46,19 +46,19 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_PINMUX] =3D { 0x40460000, 0x1000 }, [IBEX_DEV_PADCTRL] =3D { 0x40470000, 0x1000 }, [IBEX_DEV_FLASH_CTRL] =3D { 0x41000000, 0x1000 }, - [IBEX_DEV_PLIC] =3D { 0x41010000, 0x1000 }, [IBEX_DEV_AES] =3D { 0x41100000, 0x1000 }, [IBEX_DEV_HMAC] =3D { 0x41110000, 0x1000 }, [IBEX_DEV_KMAC] =3D { 0x41120000, 0x1000 }, - [IBEX_DEV_KEYMGR] =3D { 0x41130000, 0x1000 }, + [IBEX_DEV_OTBN] =3D { 0x41130000, 0x10000 }, + [IBEX_DEV_KEYMGR] =3D { 0x41140000, 0x1000 }, [IBEX_DEV_CSRNG] =3D { 0x41150000, 0x1000 }, [IBEX_DEV_ENTROPY] =3D { 0x41160000, 0x1000 }, [IBEX_DEV_EDNO] =3D { 0x41170000, 0x1000 }, [IBEX_DEV_EDN1] =3D { 0x41180000, 0x1000 }, [IBEX_DEV_ALERT_HANDLER] =3D { 0x411b0000, 0x1000 }, [IBEX_DEV_NMI_GEN] =3D { 0x411c0000, 0x1000 }, - [IBEX_DEV_OTBN] =3D { 0x411d0000, 0x10000 }, [IBEX_DEV_PERI] =3D { 0x411f0000, 0x10000 }, + [IBEX_DEV_PLIC] =3D { 0x48000000, 0x4005000 }, [IBEX_DEV_FLASH_VIRTUAL] =3D { 0x80000000, 0x80000 }, }; =20 @@ -105,7 +105,7 @@ static void lowrisc_ibex_soc_init(Object *obj) =20 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY= ); =20 - object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); + object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); =20 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); =20 @@ -145,6 +145,18 @@ static void lowrisc_ibex_soc_realize(DeviceState *de= v_soc, Error **errp) &s->flash_alias); =20 /* PLIC */ + qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); + qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0); + qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); + qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); + qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00); + qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); + qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); + qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18); + qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004); + qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4); + qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_= DEV_PLIC].size); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { return; } @@ -153,7 +165,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev= _soc, Error **errp) for (i =3D 0; i < ms->smp.cpus; i++) { CPUState *cpu =3D qemu_get_cpu(i); =20 - qdev_connect_gpio_out(DEVICE(&s->plic), i, + qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); } =20 --=20 2.31.1