From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function
Date: Fri, 22 Oct 2021 23:38:05 +1000 [thread overview]
Message-ID: <20211022133812.3972903-27-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211022133812.3972903-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
---
hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f0e2799efc..d77a5ced23 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -422,35 +422,38 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
- SiFivePLICState *plic = SIFIVE_PLIC(dev);
+ SiFivePLICState *s = SIFIVE_PLIC(dev);
int i;
- memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
- TYPE_SIFIVE_PLIC, plic->aperture_size);
- parse_hart_config(plic);
- plic->bitfield_words = (plic->num_sources + 31) >> 5;
- plic->num_enables = plic->bitfield_words * plic->num_addrs;
- plic->source_priority = g_new0(uint32_t, plic->num_sources);
- plic->target_priority = g_new(uint32_t, plic->num_addrs);
- plic->pending = g_new0(uint32_t, plic->bitfield_words);
- plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->num_enables);
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
- qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
-
- plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
- qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
-
- plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
- qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
+ memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
+ TYPE_SIFIVE_PLIC, s->aperture_size);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ parse_hart_config(s);
+
+ s->bitfield_words = (s->num_sources + 31) >> 5;
+ s->num_enables = s->bitfield_words * s->num_addrs;
+ s->source_priority = g_new0(uint32_t, s->num_sources);
+ s->target_priority = g_new(uint32_t, s->num_addrs);
+ s->pending = g_new0(uint32_t, s->bitfield_words);
+ s->claimed = g_new0(uint32_t, s->bitfield_words);
+ s->enable = g_new0(uint32_t, s->num_enables);
+
+ qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
+
+ s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+ qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
+
+ s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+ qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
/* We can't allow the supervisor to control SEIP as this would allow the
* supervisor to clear a pending external interrupt which will result in
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
* hardware controlled when a PLIC is attached.
*/
- for (i = 0; i < plic->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
+ for (i = 0; i < s->num_harts; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
error_report("SEIP already claimed");
exit(1);
--
2.31.1
next prev parent reply other threads:[~2021-10-22 14:02 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 13:37 [PULL 00/33] riscv-to-apply queue Alistair Francis
2021-10-22 13:37 ` [PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v Alistair Francis
2021-10-22 13:37 ` [PULL 02/33] target/riscv: line up all of the registers in the info register dump Alistair Francis
2021-10-22 13:37 ` [PULL 03/33] target/riscv: Fix orc.b implementation Alistair Francis
2021-10-22 13:37 ` [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory Alistair Francis
2021-10-22 13:37 ` [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh Alistair Francis
2021-10-22 13:37 ` [PULL 06/33] target/riscv: Remove some unused macros Alistair Francis
2021-10-22 13:37 ` [PULL 07/33] target/riscv: Organise the CPU properties Alistair Francis
2021-10-22 13:37 ` [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line Alistair Francis
2021-10-22 13:37 ` [PULL 09/33] target/riscv: Create RISCVMXL enumeration Alistair Francis
2021-10-22 13:37 ` [PULL 10/33] target/riscv: Split misa.mxl and misa.ext Alistair Francis
2021-10-22 13:37 ` [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Alistair Francis
2021-10-22 13:37 ` [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Alistair Francis
2021-10-22 13:37 ` [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64 Alistair Francis
2021-10-22 13:37 ` [PULL 14/33] target/riscv: Properly check SEW in amo_op Alistair Francis
2021-10-22 13:37 ` [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen Alistair Francis
2021-10-22 13:37 ` [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol Alistair Francis
2021-10-22 13:37 ` [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM Alistair Francis
2021-10-22 13:37 ` [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64 Alistair Francis
2021-10-22 13:37 ` [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB Alistair Francis
2021-10-22 13:37 ` [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI Alistair Francis
2021-10-22 13:38 ` [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump Alistair Francis
2021-10-22 13:38 ` [PULL 22/33] target/riscv: Compute mstatus.sd on demand Alistair Francis
2021-10-22 13:38 ` [PULL 23/33] hw/riscv: opentitan: Update to the latest build Alistair Francis
2021-10-22 13:38 ` [PULL 24/33] hw/intc: Remove the Ibex PLIC Alistair Francis
2021-10-22 13:38 ` [PULL 25/33] hw/intc: sifive_plic: Move the properties Alistair Francis
2021-10-22 13:38 ` Alistair Francis [this message]
2021-10-22 13:38 ` [PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function Alistair Francis
2021-10-22 13:38 ` [PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Alistair Francis
2021-10-22 13:38 ` [PULL 29/33] hw/riscv: opentitan: " Alistair Francis
2021-10-22 13:38 ` [PULL 30/33] hw/riscv: shakti_c: " Alistair Francis
2021-10-22 13:38 ` [PULL 31/33] hw/riscv: sifive_e: " Alistair Francis
2021-10-22 13:38 ` [PULL 32/33] hw/riscv: sifive_u: " Alistair Francis
2021-10-22 13:38 ` [PULL 33/33] hw/riscv: spike: " Alistair Francis
2021-10-22 21:39 ` [PULL 00/33] riscv-to-apply queue Richard Henderson
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