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Fri, 22 Oct 2021 06:41:17 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.39]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HbQVJ3Rf7z1RtVl; Fri, 22 Oct 2021 06:41:11 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Igor Mammedov Subject: [PULL 31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id Date: Fri, 22 Oct 2021 23:38:10 +1000 Message-Id: <20211022133812.3972903-32-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211022133812.3972903-1-alistair.francis@opensource.wdc.com> References: <20211022133812.3972903-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=9222bbd82=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 6e95ea5896..9b206407a6 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -29,6 +29,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" @@ -71,22 +72,27 @@ static const MemMapEntry sifive_e_memmap[] =3D { =20 static void sifive_e_machine_init(MachineState *machine) { + MachineClass *mc =3D MACHINE_GET_CLASS(machine); const MemMapEntry *memmap =3D sifive_e_memmap; =20 SiFiveEState *s =3D RISCV_E_MACHINE(machine); MemoryRegion *sys_mem =3D get_system_memory(); - MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); int i; =20 + if (machine->ram_size !=3D mc->default_ram_size) { + char *sz =3D size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_= E_SOC); qdev_realize(DEVICE(&s->soc), NULL, &error_abort); =20 /* Data Tightly Integrated Memory */ - memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", - memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_DEV_DTIM].base, main_mem); + memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); =20 /* Mask ROM reset vector */ uint32_t reset_vec[4]; @@ -142,6 +148,8 @@ static void sifive_e_machine_class_init(ObjectClass *= oc, void *data) mc->init =3D sifive_e_machine_init; mc->max_cpus =3D 1; mc->default_cpu_type =3D SIFIVE_E_CPU; + mc->default_ram_id =3D "riscv.sifive.e.ram"; + mc->default_ram_size =3D sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; =20 object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb= , sifive_e_machine_set_revb); --=20 2.31.1