From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 0/3] target/mips: MSA opcode fixes
Date: Fri, 22 Oct 2021 19:45:47 +0200 [thread overview]
Message-ID: <20211022174550.36937-1-f4bug@amsat.org> (raw)
Fix a pair of MSA opcodes, and update the MSA_IR config register
in the Loongson-3A4000 model.
Philippe Mathieu-Daudé (3):
target/mips: Fix MSA MADDV.B opcode
target/mips: Fix MSA MSUBV.B opcode
target/mips: Fix Loongson-3A4000 MSAIR config register
target/mips/tcg/msa_helper.c | 64 ++++++++++++++++++------------------
target/mips/cpu-defs.c.inc | 1 +
2 files changed, 33 insertions(+), 32 deletions(-)
--
2.31.1
next reply other threads:[~2021-10-22 17:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 17:45 Philippe Mathieu-Daudé [this message]
2021-10-22 17:45 ` [PATCH 1/3] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-22 21:41 ` Richard Henderson
2021-10-22 17:45 ` [PATCH 2/3] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-22 21:42 ` Richard Henderson
2021-10-22 17:45 ` [PATCH 3/3] target/mips: Fix Loongson-3A4000 MSAIR config register Philippe Mathieu-Daudé
2021-10-23 7:38 ` Philippe Mathieu-Daudé
2021-10-23 12:31 ` Jiaxun Yang
2021-10-26 18:08 ` [PATCH 0/3] target/mips: MSA opcode fixes Philippe Mathieu-Daudé
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