From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com,
kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs
Date: Mon, 25 Oct 2021 20:36:06 +0300 [thread overview]
Message-ID: <20211025173609.2724490-6-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20211025173609.2724490-1-space.monkey.delivers@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b767a4a0b..16fac64806 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -271,6 +271,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CSR_MSCRATCH,
CSR_SSCRATCH,
CSR_SATP,
+ CSR_MMTE,
+ CSR_UPMBASE,
+ CSR_UPMMASK,
+ CSR_SPMBASE,
+ CSR_SPMMASK,
+ CSR_MPMBASE,
+ CSR_MPMMASK,
};
for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
--
2.30.2
next prev parent reply other threads:[~2021-10-25 17:41 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 17:36 [PATCH v17 0/8] RISC-V Pointer Masking implementation Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 1/8] target/riscv: Add J-extension into RISC-V Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 2/8] target/riscv: Add CSR defines for RISC-V PM extension Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 3/8] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-10-25 18:46 ` Richard Henderson
2021-10-25 17:36 ` [PATCH v17 4/8] target/riscv: Add J extension state description Alexey Baturo
2021-10-25 17:36 ` Alexey Baturo [this message]
2021-10-25 22:32 ` [PATCH v17 5/8] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-25 17:36 ` [PATCH v17 6/8] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 7/8] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-10-25 17:36 ` [PATCH v17 8/8] target/riscv: Allow experimental J-ext to be turned on Alexey Baturo
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