From: Atish Patra <atish.patra@wdc.com>
To: qemu-devel@nongnu.org
Cc: Atish Patra <atish.patra@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
Date: Mon, 25 Oct 2021 12:55:53 -0700 [thread overview]
Message-ID: <20211025195601.245631-3-atish.patra@wdc.com> (raw)
In-Reply-To: <20211025195601.245631-1-atish.patra@wdc.com>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ec776013435..de484c74d3b4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
+ int ctr_index;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_is_32bit(env)) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.31.1
next prev parent reply other threads:[~2021-10-25 19:58 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
2021-11-03 5:40 ` Alistair Francis
2021-11-04 11:00 ` Bin Meng
2021-10-25 19:55 ` Atish Patra [this message]
2021-11-03 5:43 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Alistair Francis
2021-11-04 11:07 ` Bin Meng
2022-01-05 21:46 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2021-11-03 5:47 ` Alistair Francis
2021-11-04 11:10 ` Bin Meng
2022-01-05 21:48 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
2021-11-03 5:50 ` Alistair Francis
2021-11-04 11:45 ` Bin Meng
2022-01-05 21:51 ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
2021-11-03 5:51 ` Alistair Francis
2021-11-04 11:49 ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2021-10-25 19:55 ` [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation Atish Patra
2021-10-25 19:55 ` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support Atish Patra
2021-12-27 4:37 ` Frank Chang
2022-01-07 0:38 ` Atish Patra
2021-10-25 19:56 ` [ PATCH v3 09/10] target/riscv: Add few cache related PMU events Atish Patra
2021-10-25 19:56 ` [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
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