From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v2 2/4] target/arm: Introduce store_cpu_field_constant() helper
Date: Wed, 27 Oct 2021 06:56:05 +0200 [thread overview]
Message-ID: <20211027045607.1261526-3-f4bug@amsat.org> (raw)
In-Reply-To: <20211027045607.1261526-1-f4bug@amsat.org>
Similarly to the store_cpu_field() helper which takes a TCG
temporary, store its value to the CPUState, introduce the
store_cpu_field_constant() helper which store a constant to
CPUState (without using any TCG temporary).
Update the single store_cpu_offset() user in do_coproc_insn().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/translate-a32.h | 11 ++++++++---
target/arm/translate.c | 2 +-
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index 88f15df60e8..2e708ca3dbc 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -61,14 +61,19 @@ static inline TCGv_i32 load_cpu_offset(int offset)
#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
-static inline void store_cpu_offset(TCGv_i32 var, int offset)
+static inline void store_cpu_offset(TCGv_i32 var, int offset, bool is_temp)
{
tcg_gen_st_i32(var, cpu_env, offset);
- tcg_temp_free_i32(var);
+ if (is_temp) {
+ tcg_temp_free_i32(var);
+ }
}
#define store_cpu_field(var, name) \
- store_cpu_offset(var, offsetof(CPUARMState, name))
+ store_cpu_offset(var, offsetof(CPUARMState, name), true)
+
+#define store_cpu_field_constant(val, name) \
+ store_cpu_offset(tcg_constant_i32(val), offsetof(CPUARMState, name), false)
/* Create a new temporary and set it to the value of a CPU register. */
static inline TCGv_i32 load_reg(DisasContext *s, int reg)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 083a6d6ed77..5061e55f2c0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4855,7 +4855,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_temp_free_i32(tmp);
} else {
TCGv_i32 tmp = load_reg(s, rt);
- store_cpu_offset(tmp, ri->fieldoffset);
+ store_cpu_offset(tmp, ri->fieldoffset, true);
}
}
}
--
2.31.1
next prev parent reply other threads:[~2021-10-27 4:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 4:56 [PATCH v2 0/4] target/arm: Use tcg_constant_* Philippe Mathieu-Daudé
2021-10-27 4:56 ` [PATCH v2 1/4] target/arm: Use tcg_constant_i32() in op_smlad() Philippe Mathieu-Daudé
2021-10-27 4:56 ` Philippe Mathieu-Daudé [this message]
2021-10-28 1:17 ` [PATCH v2 2/4] target/arm: Introduce store_cpu_field_constant() helper Richard Henderson
2021-10-29 23:07 ` Philippe Mathieu-Daudé
2021-10-27 4:56 ` [PATCH v2 3/4] target/arm: Use the constant variant of store_cpu_field() when possible Philippe Mathieu-Daudé
2021-10-27 4:56 ` [PATCH v2 4/4] target/arm: Use tcg_constant_i64() in do_sat_addsub_64() Philippe Mathieu-Daudé
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