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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id d3sm21667468wrb.36.2021.10.26.21.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 21:56:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 2/4] target/arm: Introduce store_cpu_field_constant() helper Date: Wed, 27 Oct 2021 06:56:05 +0200 Message-Id: <20211027045607.1261526-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211027045607.1261526-1-f4bug@amsat.org> References: <20211027045607.1261526-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Similarly to the store_cpu_field() helper which takes a TCG temporary, store its value to the CPUState, introduce the store_cpu_field_constant() helper which store a constant to CPUState (without using any TCG temporary). Update the single store_cpu_offset() user in do_coproc_insn(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/translate-a32.h | 11 ++++++++--- target/arm/translate.c | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 88f15df60e8..2e708ca3dbc 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -61,14 +61,19 @@ static inline TCGv_i32 load_cpu_offset(int offset) #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) -static inline void store_cpu_offset(TCGv_i32 var, int offset) +static inline void store_cpu_offset(TCGv_i32 var, int offset, bool is_temp) { tcg_gen_st_i32(var, cpu_env, offset); - tcg_temp_free_i32(var); + if (is_temp) { + tcg_temp_free_i32(var); + } } #define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUARMState, name)) + store_cpu_offset(var, offsetof(CPUARMState, name), true) + +#define store_cpu_field_constant(val, name) \ + store_cpu_offset(tcg_constant_i32(val), offsetof(CPUARMState, name), false) /* Create a new temporary and set it to the value of a CPU register. */ static inline TCGv_i32 load_reg(DisasContext *s, int reg) diff --git a/target/arm/translate.c b/target/arm/translate.c index 083a6d6ed77..5061e55f2c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4855,7 +4855,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_temp_free_i32(tmp); } else { TCGv_i32 tmp = load_reg(s, rt); - store_cpu_offset(tmp, ri->fieldoffset); + store_cpu_offset(tmp, ri->fieldoffset, true); } } } -- 2.31.1