From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree
Date: Wed, 27 Oct 2021 20:06:58 +0200 [thread overview]
Message-ID: <20211027180730.1551932-1-f4bug@amsat.org> (raw)
Since v1:
- Addressed Richard comments (thanks, I learned a lot doing so!
Although I consider this series 'boring' I enjoyed working on
your review comments).
- Included Jiaxun R-b tags, but they are conditional on Richard
ones.
v1 unchanged cover:
Hi,
This series converts 2000+ lines of switch() code to decodetree
description, so this hard-to-review/modify switch is auto generated
by the decodetree script. This is a big win for maintenance (and
indeed the convertion revealed 2 bugs).
Massive convertions are - beside being often boring - bug-prone.
In this series we re-start running the MSA tests (the tests are
run automagically in the 'build-user-static' job on gitlab CI).
Although boring, the conversion is very clean, so I hope it will
be easy enough to review. The TRANS*() macros are heavily used.
When possible, constant fields are hold with tcg_constant().
Note, various opcodes can be optimized using TCG host vectors.
We won't address that in this series, as it makes the resulting
review harder. We will post that in a following series. Here we
simply dummy-convert.
The resulting msa.decode file is quite pleasant to look at, and
the diff-stat is encouraging: number of LoC halved.
Regards,
Phil.
git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree
Based-on: <20211023164329.328137-1-f4bug@amsat.org>
Philippe Mathieu-Daudé (32):
target/mips: Fix MSA MADDV.B opcode
target/mips: Fix MSA MSUBV.B opcode
tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
target/mips: Use dup_const() to simplify
target/mips: Have check_msa_access() return a boolean
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
target/mips: Convert MSA LDI opcode to decodetree
target/mips: Convert MSA I5 instruction format to decodetree
target/mips: Convert MSA BIT instruction format to decodetree
target/mips: Convert MSA SHF opcode to decodetree
target/mips: Convert MSA I8 instruction format to decodetree
target/mips: Convert MSA load/store instruction format to decodetree
target/mips: Convert MSA 2RF instruction format to decodetree
target/mips: Convert MSA FILL opcode to decodetree
target/mips: Convert MSA 2R instruction format to decodetree
target/mips: Convert MSA VEC instruction format to decodetree
target/mips: Convert MSA 3RF instruction format to decodetree
(DF_HALF)
target/mips: Convert MSA 3RF instruction format to decodetree
(DF_WORD)
target/mips: Convert MSA 3R instruction format to decodetree (part
1/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
2/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
3/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
4/4)
target/mips: Convert MSA ELM instruction format to decodetree
target/mips: Convert MSA COPY_U opcode to decodetree
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
target/mips: Convert MSA MOVE.V opcode to decodetree
target/mips: Convert CFCMSA opcode to decodetree
target/mips: Convert CTCMSA opcode to decodetree
target/mips: Remove generic MSA opcode
target/mips: Remove one MSA unnecessary decodetree overlap group
target/mips: Adjust style in msa_translate_init()
tests/tcg/mips/ase-msa.mak | 30 +
target/mips/tcg/msa.decode | 241 ++-
target/mips/tcg/msa_helper.c | 64 +-
target/mips/tcg/msa_translate.c | 2746 +++++++---------------------
MAINTAINERS | 1 +
tests/tcg/mips/Makefile.target | 5 +
tests/tcg/mips64/Makefile.target | 9 +
tests/tcg/mips64el/Makefile.target | 12 +
tests/tcg/mipsel/Makefile.target | 9 +
9 files changed, 969 insertions(+), 2148 deletions(-)
create mode 100644 tests/tcg/mips/ase-msa.mak
create mode 100644 tests/tcg/mips64/Makefile.target
create mode 100644 tests/tcg/mips64el/Makefile.target
create mode 100644 tests/tcg/mipsel/Makefile.target
--
2.31.1
next reply other threads:[~2021-10-27 18:13 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 18:06 Philippe Mathieu-Daudé [this message]
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06 ` Richard Henderson
2021-10-28 20:53 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-27 19:17 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20 ` Richard Henderson
2021-10-28 11:04 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21 ` Richard Henderson
2021-10-28 11:45 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-27 21:46 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53 ` Richard Henderson
2021-10-28 13:14 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02 ` Richard Henderson
2021-10-28 13:40 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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