From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format to decodetree
Date: Wed, 27 Oct 2021 20:07:07 +0200 [thread overview]
Message-ID: <20211027180730.1551932-10-f4bug@amsat.org> (raw)
In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org>
Convert instructions with a 5-bit immediate value to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- add &msa_i5 format
- TRANS_MSA() calls check_msa_enabled()
- TCG timm is constant
---
target/mips/tcg/msa.decode | 16 +++++
target/mips/tcg/msa_translate.c | 114 ++++++++++----------------------
2 files changed, 52 insertions(+), 78 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index bdfe5a24cb3..115e90b4fce 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -15,10 +15,13 @@
&msa_bz df wt sa
&msa_ldi df wd sa
+&msa_i5 df wd ws sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
+@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
@@ -30,6 +33,19 @@ BZ 010001 110 .. ..... ................ @bz
BNZ 010001 111 .. ..... ................ @bz
{
+ ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
+ SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
+ MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
+ MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
+ MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
+ MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
+
+ CEQI 011110 000 .. ..... ..... ..... 000111 @s5
+ CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
+ CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
+ CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
+ CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
+
LDI 011110 110 .. .......... ..... 000111 @ldi
MSA 011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 46f5ba092e1..ca70c38c866 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -27,8 +27,6 @@ enum {
OPC_MSA_I8_00 = 0x00 | OPC_MSA,
OPC_MSA_I8_01 = 0x01 | OPC_MSA,
OPC_MSA_I8_02 = 0x02 | OPC_MSA,
- OPC_MSA_I5_06 = 0x06 | OPC_MSA,
- OPC_MSA_I5_07 = 0x07 | OPC_MSA,
OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
@@ -58,19 +56,6 @@ enum {
};
enum {
- /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
- OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
- OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
- OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
- OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
- OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
- OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
- OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
- OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
- OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
-
/* I8 instruction */
OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
@@ -312,6 +297,22 @@ static inline bool check_msa_enabled(DisasContext *ctx)
return true;
}
+typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
+
+/*
+ * Helpers for implementing sets of trans_* functions.
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
+ * All helpers check whether MSA is enabled.
+ */
+#define TRANS_MSA(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { \
+ if (!check_msa_enabled(ctx)) { \
+ return true; \
+ } \
+ return FUNC(ctx, a, __VA_ARGS__); \
+ }
+
static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
TCGCond cond)
{
@@ -461,69 +462,30 @@ static void gen_msa_i8(DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
-static void gen_msa_i5(DisasContext *ctx)
+static bool trans_msa_i5(DisasContext *ctx, arg_msa_i5 *a,
+ gen_helper_piiii *gen_msa_i5)
{
-#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
- uint8_t u5 = extract32(ctx->opcode, 16, 5);
+ gen_msa_i5(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->sa));
- TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
- TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
- TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
- TCGv_i32 timm = tcg_temp_new_i32();
- tcg_gen_movi_i32(timm, u5);
-
- switch (MASK_MSA_I5(ctx->opcode)) {
- case OPC_ADDVI_df:
- gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_SUBVI_df:
- gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MAXI_U_df:
- gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_MINI_U_df:
- gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CEQI_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLTI_U_df:
- gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_S_df:
- tcg_gen_movi_i32(timm, s5);
- gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
- break;
- case OPC_CLEI_U_df:
- gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
-
- tcg_temp_free_i32(tdf);
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(timm);
+ return true;
}
+TRANS_MSA(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df);
+TRANS_MSA(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df);
+TRANS_MSA(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df);
+TRANS_MSA(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df);
+TRANS_MSA(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df);
+TRANS_MSA(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df);
+TRANS_MSA(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df);
+TRANS_MSA(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df);
+TRANS_MSA(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df);
+TRANS_MSA(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df);
+TRANS_MSA(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df);
+
static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a)
{
if (!check_msa_enabled(ctx)) {
@@ -2166,10 +2128,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
case OPC_MSA_I8_02:
gen_msa_i8(ctx);
break;
- case OPC_MSA_I5_06:
- case OPC_MSA_I5_07:
- gen_msa_i5(ctx);
- break;
case OPC_MSA_BIT_09:
case OPC_MSA_BIT_0A:
gen_msa_bit(ctx);
--
2.31.1
next prev parent reply other threads:[~2021-10-27 18:43 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06 ` Richard Henderson
2021-10-28 20:53 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10 ` Richard Henderson
2021-10-27 18:07 ` Philippe Mathieu-Daudé [this message]
2021-10-27 19:17 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20 ` Richard Henderson
2021-10-28 11:04 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21 ` Richard Henderson
2021-10-28 11:45 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-27 21:46 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53 ` Richard Henderson
2021-10-28 13:14 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02 ` Richard Henderson
2021-10-28 13:40 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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