From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 15/32] target/mips: Convert MSA FILL opcode to decodetree
Date: Wed, 27 Oct 2021 20:07:13 +0200 [thread overview]
Message-ID: <20211027180730.1551932-16-f4bug@amsat.org> (raw)
In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org>
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2:
- check TARGET_LONG_BITS != 64 before check_msa_access()
- !check_msa_access returns true
- Use tcg_constant_i32()
---
target/mips/tcg/msa.decode | 2 ++
target/mips/tcg/msa_translate.c | 32 ++++++++++++++++++++------------
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 395a2cbafeb..030ffa9321b 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -28,6 +28,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@@ -83,6 +84,7 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FILL 011110 11000000 .. ..... ..... 011110 @2r
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index a61ba9a4db8..004eb0b7700 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -56,7 +56,6 @@ enum {
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
- OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
@@ -1843,17 +1842,6 @@ static void gen_msa_2r(DisasContext *ctx)
TCGv_i32 tws = tcg_const_i32(ws);
switch (MASK_MSA_2R(ctx->opcode)) {
- case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
- twd, tws); /* trs */
- break;
case OPC_NLOC_df:
switch (df) {
case DF_BYTE:
@@ -1912,6 +1900,26 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(tws);
}
+static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
+{
+ if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
+ /* Double format valid only for MIPS64 */
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_fill_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws));
+
+ return true;
+}
+
static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
gen_helper_piii *gen_msa_2rf)
{
--
2.31.1
next prev parent reply other threads:[~2021-10-27 18:31 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06 ` Richard Henderson
2021-10-28 20:53 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-27 19:17 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20 ` Richard Henderson
2021-10-28 11:04 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21 ` Richard Henderson
2021-10-28 11:45 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` Philippe Mathieu-Daudé [this message]
2021-10-27 21:46 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53 ` Richard Henderson
2021-10-28 13:14 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02 ` Richard Henderson
2021-10-28 13:40 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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