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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode
Date: Wed, 27 Oct 2021 20:06:59 +0200	[thread overview]
Message-ID: <20211027180730.1551932-2-f4bug@amsat.org> (raw)
In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org>

The result of the 'Vector Multiply and Add' opcode is incorrect
with Byte vectors. Probably due to a copy/paste error, commit
7a7a162adde mistakenly used the $wt (target register) instead
of $wd (destination register) as first operand. Fix that.

Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_helper.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index e40c1b70575..d978909527f 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env,
     wr_t *pws = &(env->active_fpu.fpr[ws].wr);
     wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
 
-    pwd->b[0]  = msa_maddv_df(DF_BYTE, pwt->b[0],  pws->b[0],  pwt->b[0]);
-    pwd->b[1]  = msa_maddv_df(DF_BYTE, pwt->b[1],  pws->b[1],  pwt->b[1]);
-    pwd->b[2]  = msa_maddv_df(DF_BYTE, pwt->b[2],  pws->b[2],  pwt->b[2]);
-    pwd->b[3]  = msa_maddv_df(DF_BYTE, pwt->b[3],  pws->b[3],  pwt->b[3]);
-    pwd->b[4]  = msa_maddv_df(DF_BYTE, pwt->b[4],  pws->b[4],  pwt->b[4]);
-    pwd->b[5]  = msa_maddv_df(DF_BYTE, pwt->b[5],  pws->b[5],  pwt->b[5]);
-    pwd->b[6]  = msa_maddv_df(DF_BYTE, pwt->b[6],  pws->b[6],  pwt->b[6]);
-    pwd->b[7]  = msa_maddv_df(DF_BYTE, pwt->b[7],  pws->b[7],  pwt->b[7]);
-    pwd->b[8]  = msa_maddv_df(DF_BYTE, pwt->b[8],  pws->b[8],  pwt->b[8]);
-    pwd->b[9]  = msa_maddv_df(DF_BYTE, pwt->b[9],  pws->b[9],  pwt->b[9]);
-    pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]);
-    pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]);
-    pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]);
-    pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]);
-    pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]);
-    pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]);
+    pwd->b[0]  = msa_maddv_df(DF_BYTE, pwd->b[0],  pws->b[0],  pwt->b[0]);
+    pwd->b[1]  = msa_maddv_df(DF_BYTE, pwd->b[1],  pws->b[1],  pwt->b[1]);
+    pwd->b[2]  = msa_maddv_df(DF_BYTE, pwd->b[2],  pws->b[2],  pwt->b[2]);
+    pwd->b[3]  = msa_maddv_df(DF_BYTE, pwd->b[3],  pws->b[3],  pwt->b[3]);
+    pwd->b[4]  = msa_maddv_df(DF_BYTE, pwd->b[4],  pws->b[4],  pwt->b[4]);
+    pwd->b[5]  = msa_maddv_df(DF_BYTE, pwd->b[5],  pws->b[5],  pwt->b[5]);
+    pwd->b[6]  = msa_maddv_df(DF_BYTE, pwd->b[6],  pws->b[6],  pwt->b[6]);
+    pwd->b[7]  = msa_maddv_df(DF_BYTE, pwd->b[7],  pws->b[7],  pwt->b[7]);
+    pwd->b[8]  = msa_maddv_df(DF_BYTE, pwd->b[8],  pws->b[8],  pwt->b[8]);
+    pwd->b[9]  = msa_maddv_df(DF_BYTE, pwd->b[9],  pws->b[9],  pwt->b[9]);
+    pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
+    pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
+    pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
+    pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
+    pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
+    pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
 }
 
 void helper_msa_maddv_h(CPUMIPSState *env,
-- 
2.31.1



  reply	other threads:[~2021-10-27 18:18 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` Philippe Mathieu-Daudé [this message]
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06   ` Richard Henderson
2021-10-28 20:53     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-27 19:17   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20   ` Richard Henderson
2021-10-28 11:04     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21   ` Richard Henderson
2021-10-28 11:45     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-27 21:46   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53   ` Richard Henderson
2021-10-28 13:14     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02   ` Richard Henderson
2021-10-28 13:40     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé

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