qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
Date: Wed, 27 Oct 2021 20:07:04 +0200	[thread overview]
Message-ID: <20211027180730.1551932-7-f4bug@amsat.org> (raw)
In-Reply-To: <20211027180730.1551932-1-f4bug@amsat.org>

Replace magic DataFormat value by the corresponding
enum from CPUMIPSMSADataFormat.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5acb27f1d71..41ade61879e 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1789,10 +1789,10 @@ static void gen_msa_3rf(DisasContext *ctx)
     case OPC_MULR_Q_df:
     case OPC_MADDR_Q_df:
     case OPC_MSUBR_Q_df:
-        tdf = tcg_constant_i32(df + 1);
+        tdf = tcg_constant_i32(DF_HALF + df);
         break;
     default:
-        tdf = tcg_constant_i32(df + 2);
+        tdf = tcg_constant_i32(DF_WORD + df);
         break;
     }
 
@@ -2021,7 +2021,7 @@ static void gen_msa_2rf(DisasContext *ctx)
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
     /* adjust df value for floating-point instruction */
-    TCGv_i32 tdf = tcg_constant_i32(df + 2);
+    TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
 
     switch (MASK_MSA_2RF(ctx->opcode)) {
     case OPC_FCLASS_df:
-- 
2.31.1



  parent reply	other threads:[~2021-10-27 18:19 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06   ` Richard Henderson
2021-10-28 20:53     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07   ` Richard Henderson
2021-10-27 18:07 ` Philippe Mathieu-Daudé [this message]
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-27 19:17   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20   ` Richard Henderson
2021-10-28 11:04     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21   ` Richard Henderson
2021-10-28 11:45     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-27 21:46   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53   ` Richard Henderson
2021-10-28 13:14     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02   ` Richard Henderson
2021-10-28 13:40     ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08   ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211027180730.1551932-7-f4bug@amsat.org \
    --to=f4bug@amsat.org \
    --cc=aleksandar.rikalo@syrmia.com \
    --cc=aurelien@aurel32.net \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).