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Wed, 27 Oct 2021 21:45:02 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.165.40]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HftJp1B56z1RtVl; Wed, 27 Oct 2021 21:44:57 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Alexey Baturo , Alistair Francis , Bin Meng , Richard Henderson Subject: [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on Date: Thu, 28 Oct 2021 14:43:38 +1000 Message-Id: <20211028044342.3070385-15-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com> References: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=928ee31ee=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16fac64806..7d53125dbc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,6 +562,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_j) { + ext |=3D RVJ; + } =20 set_misa(env, env->misa_mxl, ext); } @@ -637,6 +640,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), --=20 2.31.1