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Wed, 27 Oct 2021 21:44:02 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.165.40]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HftHg22FLz1RtVl; Wed, 27 Oct 2021 21:43:58 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PULL 02/18] hw/riscv: boot: Add a PLIC config string function Date: Thu, 28 Oct 2021 14:43:26 +1000 Message-Id: <20211028044342.3070385-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com> References: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=928ee31ee=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add a generic function that can create the PLIC strings. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com --- include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 25 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 0e89400b09..baff11dd8a 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -31,6 +31,8 @@ =20 bool riscv_is_32bit(RISCVHartArrayState *harts); =20 +char *riscv_plic_hart_config_string(int hart_count); + target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr= ); target_ulong riscv_find_and_load_firmware(MachineState *machine, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d1ffc7b56c..519fa455a1 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -38,6 +38,31 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) return harts->harts[0].env.misa_mxl_max =3D=3D MXL_RV32; } =20 +/* + * Return the per-socket PLIC hart topology configuration string + * (caller must free with g_free()) + */ +char *riscv_plic_hart_config_string(int hart_count) +{ + g_autofree const char **vals =3D g_new(const char *, hart_count + 1)= ; + int i; + + for (i =3D 0; i < hart_count; i++) { + CPUState *cs =3D qemu_get_cpu(i); + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVS)) { + vals[i] =3D "MS"; + } else { + vals[i] =3D "M"; + } + } + vals[i] =3D NULL; + + /* g_strjoinv() obliges us to cast away const here */ + return g_strjoinv(",", (char **)vals); +} + target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr= ) { if (riscv_is_32bit(harts)) { --=20 2.31.1