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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n9sm3728728wmq.6.2021.10.28.14.09.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:38 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 11/32] target/mips: Convert MSA SHF opcode to decodetree Date: Thu, 28 Oct 2021 23:08:22 +0200 Message-Id: <20211028210843.2120802-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- v3: - Renamed &msa_i8 -> &msa_i - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 36 +++++++++++++++++---------------- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 3d6c6faf688..8e887f54ad5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -26,6 +26,7 @@ @bz ...... ... df:2 wt:5 sa:16 &msa_bz @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i +@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi @bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m @@ -38,6 +39,8 @@ BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz { + SHF 011110 .. ........ ..... ..... 000010 @i8_df + ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index cd86d6cc5c0..c776735f7c6 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -60,13 +60,10 @@ enum { /* I8 instruction */ OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00, OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01, - OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02, OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00, OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01, - OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02, OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00, OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01, - OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02, OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00, /* VEC/2R/2RF instruction */ @@ -463,20 +460,6 @@ static void gen_msa_i8(DisasContext *ctx) case OPC_BSELI_B: gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); break; - case OPC_SHF_B: - case OPC_SHF_H: - case OPC_SHF_W: - { - uint8_t df = (ctx->opcode >> 24) & 0x3; - if (df == DF_DOUBLE) { - gen_reserved_instruction(ctx); - } else { - TCGv_i32 tdf = tcg_const_i32(df); - gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); - tcg_temp_free_i32(tdf); - } - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -488,6 +471,25 @@ static void gen_msa_i8(DisasContext *ctx) tcg_temp_free_i32(ti8); } +static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) +{ + if (a->df == DF_DOUBLE) { + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_shf_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; +} + static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, gen_helper_piiii *gen_msa_i5) { -- 2.31.1