From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH v3 14/32] target/mips: Convert MSA 2RF instruction format to decodetree
Date: Thu, 28 Oct 2021 23:08:25 +0200 [thread overview]
Message-ID: <20211028210843.2120802-15-f4bug@amsat.org> (raw)
In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org>
Convert 2-register floating-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v3:
- Add plus_2(), extract DF in decoder
- Remove TRANS_MSA(), call check_msa_enabled in trans_X()
---
target/mips/tcg/msa.decode | 20 ++++++
target/mips/tcg/msa_translate.c | 118 +++++++++-----------------------
2 files changed, 53 insertions(+), 85 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 0aeb83d5c5b..33288b50355 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,6 +13,7 @@
&r rs rt rd sa
+&msa_r df wd ws wt
&msa_bz df wt sa
&msa_ldi df wd sa
&msa_i df wd ws sa
@@ -20,11 +21,13 @@
%bit_df 16:7 !function=bit_df
%bit_m 16:7 !function=bit_m
+%2r_df_w 16:1 !function=plus_2
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i
@@ -79,6 +82,23 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FCLASS 011110 110010000 . ..... ..... 011110 @2rf
+ FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
+ FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
+ FSQRT 011110 110010011 . ..... ..... 011110 @2rf
+ FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
+ FRCP 011110 110010101 . ..... ..... 011110 @2rf
+ FRINT 011110 110010110 . ..... ..... 011110 @2rf
+ FLOG2 011110 110010111 . ..... ..... 011110 @2rf
+ FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
+ FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
+ FFQL 011110 110011010 . ..... ..... 011110 @2rf
+ FFQR 011110 110011011 . ..... ..... 011110 @2rf
+ FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
+ FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
+ FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
+ FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
+
LD 011110 .......... ..... ..... 1000 .. @ldst
ST 011110 .......... ..... ..... 1001 .. @ldst
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 53cafe53f14..477eba49ac4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -20,6 +20,11 @@
static int bit_m(DisasContext *ctx, int x);
static int bit_df(DisasContext *ctx, int x);
+static inline int plus_2(DisasContext *s, int x)
+{
+ return x + 2;
+}
+
/* Include the auto-generated decoder. */
#include "decode-msa.c.inc"
@@ -44,7 +49,7 @@ enum {
};
enum {
- /* VEC/2R/2RF instruction */
+ /* VEC/2R instruction */
OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
@@ -54,7 +59,6 @@ enum {
OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
- OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
@@ -62,24 +66,6 @@ enum {
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
- /* 2RF instruction df(bit 16) = _w, _d */
- OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
- OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
- OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
- OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
- OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
- OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
- OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
- OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
- OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
- OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
- OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
- OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
- OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
- OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
- OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
-
/* 3R instruction df(bits 22..21) = _b, _h, _w, d */
OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
@@ -1928,73 +1914,38 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(tws);
}
-static void gen_msa_2rf(DisasContext *ctx)
+static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_piii *gen_msa_2rf)
{
-#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
- (op & (0xf << 17)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 16) & 0x1;
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- /* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
-
- switch (MASK_MSA_2RF(ctx->opcode)) {
- case OPC_FCLASS_df:
- gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_S_df:
- gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTRUNC_U_df:
- gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FSQRT_df:
- gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRSQRT_df:
- gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRCP_df:
- gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FRINT_df:
- gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FLOG2_df:
- gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPL_df:
- gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FEXUPR_df:
- gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQL_df:
- gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFQR_df:
- gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_S_df:
- gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FTINT_U_df:
- gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_S_df:
- gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
- break;
- case OPC_FFINT_U_df:
- gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
- break;
+ if (!check_msa_enabled(ctx)) {
+ return true;
}
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
+ gen_msa_2rf(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws));
+
+ return true;
}
+TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df);
+TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df);
+TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df);
+TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df);
+TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df);
+TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df);
+TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df);
+TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df);
+TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df);
+TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df);
+TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df);
+TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df);
+TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);
+TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);
+TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);
+
static void gen_msa_vec_v(DisasContext *ctx)
{
#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
@@ -2053,9 +2004,6 @@ static void gen_msa_vec(DisasContext *ctx)
case OPC_MSA_2R:
gen_msa_2r(ctx);
break;
- case OPC_MSA_2RF:
- gen_msa_2rf(ctx);
- break;
default:
MIPS_INVAL("MSA instruction");
gen_reserved_instruction(ctx);
--
2.31.1
next prev parent reply other threads:[~2021-10-28 21:32 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 21:08 [PATCH v3 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-29 16:12 ` Richard Henderson
2021-11-02 12:32 ` Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-29 16:13 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-29 16:14 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-28 21:08 ` Philippe Mathieu-Daudé [this message]
2021-10-28 21:08 ` [PATCH v3 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-29 16:29 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-29 16:35 ` Richard Henderson
2021-10-29 17:23 ` Philippe Mathieu-Daudé
2021-10-29 17:50 ` Richard Henderson
2021-11-02 12:31 ` Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-29 16:37 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-29 16:42 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-11-02 12:36 ` [PATCH v3 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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