From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH v3 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Date: Thu, 28 Oct 2021 23:08:31 +0200 [thread overview]
Message-ID: <20211028210843.2120802-21-f4bug@amsat.org> (raw)
In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org>
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v3:
- Remove TRANS_MSA(), call check_msa_enabled in trans_X()
---
target/mips/tcg/msa.decode | 6 ++++++
target/mips/tcg/msa_translate.c | 17 +++++------------
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 1d6ada4c142..4b14acce26f 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -32,6 +32,7 @@
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
+@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
@@ -88,6 +89,11 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ SLD 011110 000 .. ..... ..... ..... 010100 @3r
+ SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
+
+ VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index fbaf9f622f3..6738a2b8cd7 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -58,15 +58,12 @@ enum {
OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
- OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
- OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
- OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -503,6 +500,11 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v);
TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v);
TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v);
+TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df);
+TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df);
+
+TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df);
+
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -1253,12 +1255,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SLD_df:
- gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_VSHF_df:
- gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBV_df:
switch (df) {
case DF_BYTE:
@@ -1291,9 +1287,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SPLAT_df:
- gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUS_U_df:
switch (df) {
case DF_BYTE:
--
2.31.1
next prev parent reply other threads:[~2021-10-28 21:25 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 21:08 [PATCH v3 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-29 16:12 ` Richard Henderson
2021-11-02 12:32 ` Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-29 16:13 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-29 16:14 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-29 16:29 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-28 21:08 ` Philippe Mathieu-Daudé [this message]
2021-10-29 16:35 ` [PATCH v3 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Richard Henderson
2021-10-29 17:23 ` Philippe Mathieu-Daudé
2021-10-29 17:50 ` Richard Henderson
2021-11-02 12:31 ` Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-29 16:37 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-29 16:42 ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-11-02 12:36 ` [PATCH v3 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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