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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH v3 04/32] target/mips: Use dup_const() to simplify
Date: Thu, 28 Oct 2021 23:08:15 +0200	[thread overview]
Message-ID: <20211028210843.2120802-5-f4bug@amsat.org> (raw)
In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org>

The dup_const() helper makes the code easier to follow, use it.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v3: Fix eval_big
---
 target/mips/tcg/msa_translate.c | 23 +++--------------------
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..6fefb06da7c 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -313,28 +313,11 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
 {
     /* generates tcg ops to check if any element is 0 */
     /* Note this function only works with MSA_WRLEN = 128 */
-    uint64_t eval_zero_or_big = 0;
-    uint64_t eval_big = 0;
+    uint64_t eval_zero_or_big = dup_const(df, 1);
+    uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1);
     TCGv_i64 t0 = tcg_temp_new_i64();
     TCGv_i64 t1 = tcg_temp_new_i64();
-    switch (df) {
-    case DF_BYTE:
-        eval_zero_or_big = 0x0101010101010101ULL;
-        eval_big = 0x8080808080808080ULL;
-        break;
-    case DF_HALF:
-        eval_zero_or_big = 0x0001000100010001ULL;
-        eval_big = 0x8000800080008000ULL;
-        break;
-    case DF_WORD:
-        eval_zero_or_big = 0x0000000100000001ULL;
-        eval_big = 0x8000000080000000ULL;
-        break;
-    case DF_DOUBLE:
-        eval_zero_or_big = 0x0000000000000001ULL;
-        eval_big = 0x8000000000000000ULL;
-        break;
-    }
+
     tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big);
     tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]);
     tcg_gen_andi_i64(t0, t0, eval_big);
-- 
2.31.1



  parent reply	other threads:[~2021-10-28 21:11 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-28 21:08 [PATCH v3 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-29 16:12   ` Richard Henderson
2021-11-02 12:32     ` Philippe Mathieu-Daudé
2021-10-28 21:08 ` Philippe Mathieu-Daudé [this message]
2021-10-29 16:13   ` [PATCH v3 04/32] target/mips: Use dup_const() to simplify Richard Henderson
2021-10-28 21:08 ` [PATCH v3 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-29 16:14   ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-29 16:29   ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-29 16:35   ` Richard Henderson
2021-10-29 17:23     ` Philippe Mathieu-Daudé
2021-10-29 17:50       ` Richard Henderson
2021-11-02 12:31         ` Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-29 16:37   ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-29 16:42   ` Richard Henderson
2021-10-28 21:08 ` [PATCH v3 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-28 21:08 ` [PATCH v3 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-11-02 12:36 ` [PATCH v3 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé

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