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Fri, 29 Oct 2021 00:10:00 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.42]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HgYTJ5rpPz1RtVl; Fri, 29 Oct 2021 00:08:59 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis Subject: [PULL v2 00/18] riscv-to-apply queue Date: Fri, 29 Oct 2021 17:07:59 +1000 Message-Id: <20211029070817.100529-1-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=929275e61=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c3016= 1d: Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-2021102= 7' into staging (2021-10-27 11:45:18 -0700) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211029-1 for you to fetch changes up to 15161e425ee1bb1180f9cec574cda44fb10c0931: target/riscv: change the api for RVF/RVD fmin/fmax (2021-10-29 16:56:12= +1000) ---------------------------------------------------------------- Fifth RISC-V PR for QEMU 6.2 - Use a shared PLIC config helper function - Fixup the OpenTitan PLIC configuration - Add support for the experimental J extension - Update the fmin/fmax handling - Fixup VS interrupt forwarding ---------------------------------------------------------------- Alexey Baturo (7): target/riscv: Add J-extension into RISC-V target/riscv: Add CSR defines for RISC-V PM extension target/riscv: Support CSRs required for RISC-V PM extension except = for the h-mode target/riscv: Add J extension state description target/riscv: Print new PM CSRs in QEMU logs target/riscv: Support pointer masking for RISC-V for i/c/f/d/a type= s of instructions target/riscv: Allow experimental J-ext to be turned on Alistair Francis (6): hw/riscv: virt: Don't use a macro for the PLIC configuration hw/riscv: boot: Add a PLIC config string function hw/riscv: sifive_u: Use the PLIC config helper function hw/riscv: microchip_pfsoc: Use the PLIC config helper function hw/riscv: virt: Use the PLIC config helper function hw/riscv: opentitan: Fixup the PLIC context addresses Anatoly Parshintsev (1): target/riscv: Implement address masking functions required for RISC= -V Pointer Masking extension Chih-Min Chao (2): softfloat: add APIs to handle alternative sNaN propagation for fmax= /fmin target/riscv: change the api for RVF/RVD fmin/fmax Jose Martins (2): target/riscv: fix VS interrupts forwarding to HS target/riscv: remove force HS exception include/fpu/softfloat.h | 10 ++ include/hw/riscv/boot.h | 2 + include/hw/riscv/microchip_pfsoc.h | 1 - include/hw/riscv/sifive_u.h | 1 - include/hw/riscv/virt.h | 1 - target/riscv/cpu.h | 17 +- target/riscv/cpu_bits.h | 102 +++++++++++- fpu/softfloat.c | 19 ++- hw/riscv/boot.c | 25 +++ hw/riscv/microchip_pfsoc.c | 14 +- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_u.c | 14 +- hw/riscv/virt.c | 20 +-- target/riscv/cpu.c | 13 ++ target/riscv/cpu_helper.c | 72 +++----- target/riscv/csr.c | 285 ++++++++++++++++++++++++++= ++++++ target/riscv/fpu_helper.c | 16 +- target/riscv/machine.c | 27 +++ target/riscv/translate.c | 43 +++++ fpu/softfloat-parts.c.inc | 25 ++- target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + 24 files changed, 605 insertions(+), 115 deletions(-)