From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alexey Baturo <baturo.alexey@gmail.com>,
Alexey Baturo <space.monkey.delivers@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 10/18] target/riscv: Add J extension state description
Date: Fri, 29 Oct 2021 17:08:09 +1000 [thread overview]
Message-ID: <20211029070817.100529-11-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211029070817.100529-1-alistair.francis@opensource.wdc.com>
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index f64b2a96c1..7b4c739564 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -84,6 +84,14 @@ static bool vector_needed(void *opaque)
return riscv_has_ext(env, RVV);
}
+static bool pointermasking_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVJ);
+}
+
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
.version_id = 1,
@@ -100,6 +108,24 @@ static const VMStateDescription vmstate_vector = {
}
};
+static const VMStateDescription vmstate_pointermasking = {
+ .name = "cpu/pointer_masking",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pointermasking_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.mmte, RISCVCPU),
+ VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
+ VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
+ VMSTATE_UINTTL(env.spmmask, RISCVCPU),
+ VMSTATE_UINTTL(env.spmbase, RISCVCPU),
+ VMSTATE_UINTTL(env.upmmask, RISCVCPU),
+ VMSTATE_UINTTL(env.upmbase, RISCVCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -191,6 +217,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_pmp,
&vmstate_hyper,
&vmstate_vector,
+ &vmstate_pointermasking,
NULL
}
};
--
2.31.1
next prev parent reply other threads:[~2021-10-29 7:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 7:07 [PULL v2 00/18] riscv-to-apply queue Alistair Francis
2021-10-29 7:08 ` [PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-29 7:08 ` [PULL v2 02/18] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-29 7:08 ` [PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-29 7:08 ` [PULL v2 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-29 7:08 ` [PULL v2 05/18] hw/riscv: virt: " Alistair Francis
2021-10-29 7:08 ` [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-29 7:08 ` [PULL v2 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-29 7:08 ` [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-29 7:08 ` [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-29 7:08 ` Alistair Francis [this message]
2021-10-29 7:08 ` [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-29 7:08 ` [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-29 7:08 ` [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alistair Francis
2021-10-29 7:08 ` [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-29 7:08 ` [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-29 7:08 ` [PULL v2 16/18] target/riscv: remove force HS exception Alistair Francis
2021-10-29 7:08 ` [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-29 7:08 ` [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax Alistair Francis
2021-10-29 20:53 ` [PULL v2 00/18] riscv-to-apply queue Richard Henderson
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