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Fri, 29 Oct 2021 00:15:36 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.42]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HgYc35xJ2z1RtVl; Fri, 29 Oct 2021 00:15:31 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexey Baturo , Alexey Baturo , Richard Henderson , Alistair Francis Subject: [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Date: Fri, 29 Oct 2021 17:08:11 +1000 Message-Id: <20211029070817.100529-13-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211029070817.100529-1-alistair.francis@opensource.wdc.com> References: <20211029070817.100529-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=929275e61=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, GAPPY_SUBJECT=0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis --- target/riscv/translate.c | 8 ++++++++ target/riscv/insn_trans/trans_rva.c.inc | 3 +++ target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ 5 files changed, 17 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d38f87d718..a5e6fa145d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -271,6 +271,14 @@ static void gen_jal(DisasContext *ctx, int rd, targe= t_ulong imm) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 +/* + * Temp stub: generates address adjustment for PointerMasking + */ +static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) +{ + return src; +} + #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_= trans/trans_rva.c.inc index 6ea07d89b0..40fe132b04 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Me= mOp mop) if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + src1 =3D gen_pm_adjust_address(ctx, src1); tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -44,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, Me= mOp mop) TCGLabel *l2 =3D gen_new_label(); =20 src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + src1 =3D gen_pm_adjust_address(ctx, src1); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); =20 /* @@ -84,6 +86,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 + src1 =3D gen_pm_adjust_address(ctx, src1); func(dest, src1, src2, ctx->mem_idx, mop); =20 gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_= trans/trans_rvd.c.inc index db9ae15755..64fb0046f7 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,6 +31,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } + addr =3D gen_pm_adjust_address(ctx, addr); =20 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ); =20 @@ -51,6 +52,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } + addr =3D gen_pm_adjust_address(ctx, addr); =20 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ); =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_= trans/trans_rvf.c.inc index bddbd418d9..b5459249c4 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -37,6 +37,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } + addr =3D gen_pm_adjust_address(ctx, addr); =20 dest =3D cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); @@ -59,6 +60,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } + addr =3D gen_pm_adjust_address(ctx, addr); =20 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_= trans/trans_rvi.c.inc index 91dc438a3a..e51dbc41c5 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -144,6 +144,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, Me= mOp memop) tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } + addr =3D gen_pm_adjust_address(ctx, addr); =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, dest); @@ -185,6 +186,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, M= emOp memop) tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } + addr =3D gen_pm_adjust_address(ctx, addr); =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); return true; --=20 2.31.1