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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Chih-Min Chao <chihmin.chao@sifive.com>,
	Frank Chang <frank.chang@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax
Date: Fri, 29 Oct 2021 17:08:17 +1000	[thread overview]
Message-ID: <20211029070817.100529-19-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211029070817.100529-1-alistair.francis@opensource.wdc.com>

From: Chih-Min Chao <chihmin.chao@sifive.com>

The sNaN propagation behavior has been changed since cd20cee7 in
https://github.com/riscv/riscv-isa-manual.

In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with
IEEE 754-2008 minNum and maxNum operations.

In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to
implement IEEE 754-2019 minimumNumber and maximumNumber operations.

Therefore, to prevent the risk of having too many version variables.
Instead of introducing an extra *fext_ver* variable, we tie RVF version
to Priv version. Though it's not completely accurate but is close enough.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/fpu_helper.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 8700516a14..d62f470900 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -174,14 +174,18 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
 {
     float32 frs1 = check_nanbox_s(rs1);
     float32 frs2 = check_nanbox_s(rs2);
-    return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
+    return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
+                    float32_minnum(frs1, frs2, &env->fp_status) :
+                    float32_minimum_number(frs1, frs2, &env->fp_status));
 }
 
 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
 {
     float32 frs1 = check_nanbox_s(rs1);
     float32 frs2 = check_nanbox_s(rs2);
-    return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
+    return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
+                    float32_maxnum(frs1, frs2, &env->fp_status) :
+                    float32_maximum_number(frs1, frs2, &env->fp_status));
 }
 
 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
@@ -283,12 +287,16 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 
 uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-    return float64_minnum(frs1, frs2, &env->fp_status);
+    return env->priv_ver < PRIV_VERSION_1_11_0 ?
+            float64_minnum(frs1, frs2, &env->fp_status) :
+            float64_minimum_number(frs1, frs2, &env->fp_status);
 }
 
 uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
 {
-    return float64_maxnum(frs1, frs2, &env->fp_status);
+    return env->priv_ver < PRIV_VERSION_1_11_0 ?
+            float64_maxnum(frs1, frs2, &env->fp_status) :
+            float64_maximum_number(frs1, frs2, &env->fp_status);
 }
 
 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
-- 
2.31.1



  parent reply	other threads:[~2021-10-29  7:39 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-29  7:07 [PULL v2 00/18] riscv-to-apply queue Alistair Francis
2021-10-29  7:08 ` [PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-29  7:08 ` [PULL v2 02/18] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-29  7:08 ` [PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-29  7:08 ` [PULL v2 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-29  7:08 ` [PULL v2 05/18] hw/riscv: virt: " Alistair Francis
2021-10-29  7:08 ` [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-29  7:08 ` [PULL v2 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-29  7:08 ` [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-29  7:08 ` [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-29  7:08 ` [PULL v2 10/18] target/riscv: Add J extension state description Alistair Francis
2021-10-29  7:08 ` [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-29  7:08 ` [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-29  7:08 ` [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alistair Francis
2021-10-29  7:08 ` [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-29  7:08 ` [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-29  7:08 ` [PULL v2 16/18] target/riscv: remove force HS exception Alistair Francis
2021-10-29  7:08 ` [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-29  7:08 ` Alistair Francis [this message]
2021-10-29 20:53 ` [PULL v2 00/18] riscv-to-apply queue Richard Henderson

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