From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Bin Meng" <bmeng.cn@gmail.com>
Subject: [PULL v2 02/18] hw/riscv: boot: Add a PLIC config string function
Date: Fri, 29 Oct 2021 17:08:01 +1000 [thread overview]
Message-ID: <20211029070817.100529-3-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211029070817.100529-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Add a generic function that can create the PLIC strings.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0e89400b09..baff11dd8a 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -31,6 +31,8 @@
bool riscv_is_32bit(RISCVHartArrayState *harts);
+char *riscv_plic_hart_config_string(int hart_count);
+
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index d1ffc7b56c..519fa455a1 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -38,6 +38,31 @@ bool riscv_is_32bit(RISCVHartArrayState *harts)
return harts->harts[0].env.misa_mxl_max == MXL_RV32;
}
+/*
+ * Return the per-socket PLIC hart topology configuration string
+ * (caller must free with g_free())
+ */
+char *riscv_plic_hart_config_string(int hart_count)
+{
+ g_autofree const char **vals = g_new(const char *, hart_count + 1);
+ int i;
+
+ for (i = 0; i < hart_count; i++) {
+ CPUState *cs = qemu_get_cpu(i);
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVS)) {
+ vals[i] = "MS";
+ } else {
+ vals[i] = "M";
+ }
+ }
+ vals[i] = NULL;
+
+ /* g_strjoinv() obliges us to cast away const here */
+ return g_strjoinv(",", (char **)vals);
+}
+
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr) {
if (riscv_is_32bit(harts)) {
--
2.31.1
next prev parent reply other threads:[~2021-10-29 7:17 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 7:07 [PULL v2 00/18] riscv-to-apply queue Alistair Francis
2021-10-29 7:08 ` [PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-29 7:08 ` Alistair Francis [this message]
2021-10-29 7:08 ` [PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-29 7:08 ` [PULL v2 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-29 7:08 ` [PULL v2 05/18] hw/riscv: virt: " Alistair Francis
2021-10-29 7:08 ` [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-29 7:08 ` [PULL v2 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-29 7:08 ` [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-29 7:08 ` [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-29 7:08 ` [PULL v2 10/18] target/riscv: Add J extension state description Alistair Francis
2021-10-29 7:08 ` [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-29 7:08 ` [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-29 7:08 ` [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alistair Francis
2021-10-29 7:08 ` [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-29 7:08 ` [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-29 7:08 ` [PULL v2 16/18] target/riscv: remove force HS exception Alistair Francis
2021-10-29 7:08 ` [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-29 7:08 ` [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax Alistair Francis
2021-10-29 20:53 ` [PULL v2 00/18] riscv-to-apply queue Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211029070817.100529-3-alistair.francis@opensource.wdc.com \
--to=alistair.francis@opensource.wdc.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bmeng.cn@gmail.com \
--cc=f4bug@amsat.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).