From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses
Date: Fri, 29 Oct 2021 17:08:05 +1000 [thread overview]
Message-ID: <20211029070817.100529-7-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211029070817.100529-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Fixup the PLIC context address to correctly support the threshold and
claim register.
Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com
---
hw/riscv/opentitan.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 83e1511f28..c531450b9f 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -161,8 +161,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
--
2.31.1
next prev parent reply other threads:[~2021-10-29 7:14 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 7:07 [PULL v2 00/18] riscv-to-apply queue Alistair Francis
2021-10-29 7:08 ` [PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-29 7:08 ` [PULL v2 02/18] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-29 7:08 ` [PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-29 7:08 ` [PULL v2 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-29 7:08 ` [PULL v2 05/18] hw/riscv: virt: " Alistair Francis
2021-10-29 7:08 ` Alistair Francis [this message]
2021-10-29 7:08 ` [PULL v2 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-29 7:08 ` [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-29 7:08 ` [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-29 7:08 ` [PULL v2 10/18] target/riscv: Add J extension state description Alistair Francis
2021-10-29 7:08 ` [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-29 7:08 ` [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-29 7:08 ` [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alistair Francis
2021-10-29 7:08 ` [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-29 7:08 ` [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-29 7:08 ` [PULL v2 16/18] target/riscv: remove force HS exception Alistair Francis
2021-10-29 7:08 ` [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-29 7:08 ` [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax Alistair Francis
2021-10-29 20:53 ` [PULL v2 00/18] riscv-to-apply queue Richard Henderson
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