From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Date: Fri, 29 Oct 2021 23:25:35 +0800 [thread overview]
Message-ID: <20211029152535.2055096-6-bin.meng@windriver.com> (raw)
In-Reply-To: <20211029152535.2055096-1-bin.meng@windriver.com>
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6cbe17f2e6..532c148a80 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -92,6 +92,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.25.1
next prev parent reply other threads:[~2021-10-29 15:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 15:25 [PATCH 0/5] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
2021-10-29 15:25 ` [PATCH 1/5] target/riscv: Add initial support for native debug Bin Meng
2021-10-29 19:41 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2021-10-29 19:36 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 3/5] target/riscv: Add a config option for native debug Bin Meng
2021-10-29 19:34 ` Richard Henderson
2021-10-29 15:25 ` [PATCH 4/5] target/riscv: csr: Hook debug CSR read/write Bin Meng
2021-10-29 15:25 ` Bin Meng [this message]
2021-10-29 19:33 ` [PATCH 5/5] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Richard Henderson
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