From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 2/7] target/riscv: machine: Add debug state description
Date: Sat, 30 Oct 2021 21:55:08 +0800 [thread overview]
Message-ID: <20211030135513.18517-3-bin.meng@windriver.com> (raw)
In-Reply-To: <20211030135513.18517-1-bin.meng@windriver.com>
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ad8248ebfd..25aa3b38f7 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,6 +164,38 @@ static const VMStateDescription vmstate_pointermasking = {
}
};
+static bool debug_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+
+static const VMStateDescription vmstate_debug_type2 = {
+ .name = "cpu/debug/type2",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mcontrol, trigger_type2_t),
+ VMSTATE_UINTTL(maddress, trigger_type2_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+ .name = "cpu/debug",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = debug_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+ VMSTATE_STRUCT_ARRAY(env.trigger_type2, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, trigger_type2_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
@@ -218,6 +250,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_hyper,
&vmstate_vector,
&vmstate_pointermasking,
+ &vmstate_debug,
NULL
}
};
--
2.25.1
next prev parent reply other threads:[~2021-10-30 13:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-30 13:55 [PATCH v2 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
2021-10-30 13:55 ` [PATCH v2 1/7] target/riscv: Add initial support for native debug Bin Meng
2021-10-30 13:55 ` Bin Meng [this message]
2021-11-17 0:50 ` [PATCH v2 2/7] target/riscv: machine: Add debug state description Alistair Francis
2021-10-30 13:55 ` [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2021-11-17 0:54 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2021-11-03 5:59 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2021-11-17 0:56 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs Bin Meng
2021-11-17 0:57 ` Alistair Francis
2021-11-17 9:51 ` Bin Meng
2021-10-30 13:55 ` [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2021-11-03 6:00 ` Alistair Francis
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