From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, laurent@vivier.eu, imp@bsdimp.com,
f4bug@amsat.org
Subject: [PATCH v6 66/66] target/sh4: Implement prctl_unalign_sigbus
Date: Sat, 30 Oct 2021 10:16:35 -0700 [thread overview]
Message-ID: <20211030171635.1689530-67-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211030171635.1689530-1-richard.henderson@linaro.org>
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
The Linux kernel does not handle all memory operations: no
floating-point and no MAC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sh4/target_prctl.h | 2 +-
target/sh4/cpu.h | 4 +++
target/sh4/translate.c | 50 ++++++++++++++++++++++++-----------
3 files changed, 39 insertions(+), 17 deletions(-)
diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/sh4/target_prctl.h
+++ b/linux-user/sh4/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 4cfb109f56..fb9dd9db2f 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -83,6 +83,7 @@
#define DELAY_SLOT_RTE (1 << 2)
#define TB_FLAG_PENDING_MOVCA (1 << 3)
+#define TB_FLAG_UNALIGN (1 << 4)
#define GUSA_SHIFT 4
#ifdef CONFIG_USER_ONLY
@@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
| (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
| (env->sr & (1u << SR_FD)) /* Bit 15 */
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+ *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
}
#endif /* SH4_CPU_H */
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ce5d674a52..c959ce1508 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -50,8 +50,10 @@ typedef struct DisasContext {
#if defined(CONFIG_USER_ONLY)
#define IS_USER(ctx) 1
+#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0)
#else
#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
+#define UNALIGN(C) 0
#endif
/* Target-specific values for ctx->base.is_jmp. */
@@ -495,7 +497,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -503,7 +506,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -558,19 +562,23 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
return;
case 0x2001: /* mov.w Rm,@Rn */
- tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
return;
case 0x2002: /* mov.l Rm,@Rn */
- tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
return;
case 0x6000: /* mov.b @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
return;
case 0x6001: /* mov.w @Rm,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
return;
case 0x6002: /* mov.l @Rm,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
return;
case 0x2004: /* mov.b Rm,@-Rn */
{
@@ -586,7 +594,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -595,7 +604,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -606,12 +616,14 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
return;
case 0x6005: /* mov.w @Rm+,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
return;
case 0x6006: /* mov.l @Rm+,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
return;
@@ -627,7 +639,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -635,7 +648,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -651,7 +665,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -659,7 +674,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -1253,7 +1269,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
- tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -1269,7 +1286,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
- tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
--
2.25.1
next prev parent reply other threads:[~2021-10-30 18:15 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-30 17:15 [PATCH v6 00/66] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-10-30 17:15 ` [PATCH v6 01/66] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-10-30 17:15 ` [PATCH v6 02/66] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-10-30 17:15 ` [PATCH v6 03/66] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-10-30 17:15 ` [PATCH v6 04/66] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-10-30 17:15 ` [PATCH v6 05/66] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-10-30 17:15 ` [PATCH v6 06/66] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-10-30 17:15 ` [PATCH v6 07/66] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-10-30 17:15 ` [PATCH v6 08/66] linux-user/host/ppc: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 09/66] linux-user/host/alpha: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 10/66] linux-user/host/sparc: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 11/66] linux-user/host/arm: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 12/66] linux-user/host/aarch64: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 13/66] linux-user/host/s390: " Richard Henderson
2021-11-01 16:10 ` Thomas Huth
2021-11-01 17:08 ` Richard Henderson
2021-10-30 17:15 ` [PATCH v6 14/66] linux-user/host/mips: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 15/66] linux-user/host/riscv: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 16/66] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-10-30 17:15 ` [PATCH v6 17/66] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-10-30 17:15 ` [PATCH v6 18/66] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-10-30 17:15 ` [PATCH v6 19/66] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-10-30 17:15 ` [PATCH v6 20/66] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-10-30 17:15 ` [PATCH v6 21/66] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-10-31 10:26 ` Philippe Mathieu-Daudé
2021-10-30 17:15 ` [PATCH v6 22/66] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-10-30 17:15 ` [PATCH v6 23/66] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-01 16:30 ` Peter Maydell
2021-11-01 17:09 ` Richard Henderson
2021-11-01 17:25 ` Peter Maydell
2021-11-01 17:30 ` Richard Henderson
2021-10-30 17:15 ` [PATCH v6 24/66] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:15 ` [PATCH v6 25/66] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-10-30 17:15 ` [PATCH v6 26/66] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-10-31 10:13 ` Philippe Mathieu-Daudé
2021-10-30 17:15 ` [PATCH v6 27/66] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-10-30 17:15 ` [PATCH v6 28/66] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:15 ` [PATCH v6 29/66] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-10-31 10:14 ` Philippe Mathieu-Daudé
2021-11-01 16:16 ` Edgar E. Iglesias
2021-10-30 17:15 ` [PATCH v6 30/66] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 31/66] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-10-30 17:16 ` [PATCH v6 32/66] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-10-31 10:11 ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 33/66] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 34/66] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-10-30 17:16 ` [PATCH v6 35/66] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 36/66] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-10-31 10:20 ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 37/66] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-10-30 17:16 ` [PATCH v6 38/66] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-10-31 10:21 ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 39/66] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 40/66] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 41/66] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-10-30 17:16 ` [PATCH v6 42/66] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 43/66] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 44/66] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 45/66] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-01 16:32 ` Peter Maydell
2021-10-30 17:16 ` [PATCH v6 46/66] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-10-31 10:10 ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 47/66] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 48/66] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-10-30 17:16 ` [PATCH v6 49/66] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-10-30 17:16 ` [PATCH v6 50/66] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-10-30 17:16 ` [PATCH v6 51/66] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-10-31 10:15 ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 52/66] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 53/66] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-10-30 17:16 ` [PATCH v6 54/66] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-10-30 17:16 ` [PATCH v6 55/66] target/sparc: Split out build_sfsr Richard Henderson
2021-10-30 17:16 ` [PATCH v6 56/66] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-10-30 17:16 ` [PATCH v6 57/66] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 58/66] accel/tcg: Report unaligned load/store " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 59/66] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 60/66] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
2021-10-30 17:16 ` [PATCH v6 61/66] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-10-30 17:16 ` [PATCH v6 62/66] linux-user: Disable more prctl subcodes Richard Henderson
2021-10-30 17:16 ` [PATCH v6 63/66] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
2021-10-30 17:16 ` [PATCH v6 64/66] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 65/66] target/hppa: " Richard Henderson
2021-10-30 17:16 ` Richard Henderson [this message]
2021-10-31 10:30 ` [PATCH v6 00/66] user-only: Cleanup SIGSEGV and SIGBUS handling Philippe Mathieu-Daudé
2021-10-31 13:04 ` Richard Henderson
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