From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 01/13] target/riscv: Sign extend pc for different ol
Date: Mon, 1 Nov 2021 18:01:31 +0800 [thread overview]
Message-ID: <20211101100143.44356-2-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211101100143.44356-1-zhiwei_liu@c-sky.com>
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/translate.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..7d78a3561e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -150,16 +150,31 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
}
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+ TCGv t = tcg_constant_tl(dest);
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+ tcg_gen_ext32s_tl(cpu_pc, t);
+ break;
+ case MXL_RV64:
+ tcg_gen_mov_tl(cpu_pc, t);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
static void generate_exception_mtval(DisasContext *ctx, int excp)
{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_set_pc(ctx, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
@@ -179,10 +194,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
- tcg_gen_movi_tl(cpu_pc, dest);
+ gen_set_pc(ctx, dest);
tcg_gen_lookup_and_goto_ptr();
}
}
--
2.25.1
next prev parent reply other threads:[~2021-11-01 10:11 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` LIU Zhiwei [this message]
2021-11-01 10:29 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:33 ` Richard Henderson
2021-11-02 1:48 ` LIU Zhiwei
2021-11-02 10:18 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:35 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-01 10:40 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:46 ` Richard Henderson
2021-11-01 15:56 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 13:41 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 11:35 ` Richard Henderson
2021-11-08 9:28 ` LIU Zhiwei
2021-11-09 6:37 ` Richard Henderson
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:25 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 16:33 ` Richard Henderson
2021-11-08 9:38 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 16:43 ` Richard Henderson
2021-11-08 11:23 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 16:49 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 17:01 ` Richard Henderson
2021-11-08 12:10 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
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