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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: alex.bennee@linaro.org,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, imp@bsdimp.com, laurent@vivier.eu
Subject: Re: [PATCH v6 29/66] target/microblaze: Make mb_cpu_tlb_fill sysemu only
Date: Mon, 1 Nov 2021 17:16:14 +0100	[thread overview]
Message-ID: <20211101161614.GN3586016@toto> (raw)
In-Reply-To: <33d46517-8b50-1bfb-08f6-221678579693@amsat.org>

On Sun, Oct 31, 2021 at 11:14:04AM +0100, Philippe Mathieu-Daudé wrote:
> On 10/30/21 19:15, Richard Henderson wrote:
> > The fallback code in cpu_loop_exit_sigsegv is sufficient
> > for microblaze linux-user.
> > 
> > Remove the code from cpu_loop that handled the unnamed 0xaa exception.
> > 
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> >  target/microblaze/cpu.h          |  8 ++++----
> >  linux-user/microblaze/cpu_loop.c | 10 ----------
> >  target/microblaze/cpu.c          |  2 +-
> >  target/microblaze/helper.c       | 13 +------------
> >  4 files changed, 6 insertions(+), 27 deletions(-)
> > 
> > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> > index b7a848bbae..e9cd0b88de 100644
> > --- a/target/microblaze/cpu.h
> > +++ b/target/microblaze/cpu.h
> > @@ -394,10 +394,6 @@ void mb_tcg_init(void);
> >  #define MMU_USER_IDX    2
> >  /* See NB_MMU_MODES further up the file.  */
> >  
> > -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> > -                     MMUAccessType access_type, int mmu_idx,
> > -                     bool probe, uintptr_t retaddr);
> > -
> >  typedef CPUMBState CPUArchState;
> >  typedef MicroBlazeCPU ArchCPU;
> >  
> > @@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
> >  }
> >  
> >  #if !defined(CONFIG_USER_ONLY)
> > +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> > +                     MMUAccessType access_type, int mmu_idx,
> > +                     bool probe, uintptr_t retaddr);
> > +
> >  void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
> >                                 unsigned size, MMUAccessType access_type,
> >                                 int mmu_idx, MemTxAttrs attrs,
> > diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
> > index 52222eb93f..a94467dd2d 100644
> > --- a/linux-user/microblaze/cpu_loop.c
> > +++ b/linux-user/microblaze/cpu_loop.c
> > @@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env)
> >          process_queued_cpu_work(cs);
> >  
> >          switch (trapnr) {
> > -        case 0xaa:
> > -            {
> > -                info.si_signo = TARGET_SIGSEGV;
> > -                info.si_errno = 0;
> > -                /* XXX: check env->error_code */
> > -                info.si_code = TARGET_SEGV_MAPERR;
> > -                info._sifields._sigfault._addr = 0;
> > -                queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> > -            }
> > -            break;
> >          case EXCP_INTERRUPT:
> >            /* just indicate that signals should be handled asap */
> >            break;
> > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> > index 15db277925..b9c888b87e 100644
> > --- a/target/microblaze/cpu.c
> > +++ b/target/microblaze/cpu.c
> > @@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
> >  static const struct TCGCPUOps mb_tcg_ops = {
> >      .initialize = mb_tcg_init,
> >      .synchronize_from_tb = mb_cpu_synchronize_from_tb,
> > -    .tlb_fill = mb_cpu_tlb_fill,
> >  
> >  #ifndef CONFIG_USER_ONLY
> > +    .tlb_fill = mb_cpu_tlb_fill,
> >      .cpu_exec_interrupt = mb_cpu_exec_interrupt,
> >      .do_interrupt = mb_cpu_do_interrupt,
> >      .do_transaction_failed = mb_cpu_transaction_failed,
> > diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> > index dd2aecd1d5..a607fe68e5 100644
> > --- a/target/microblaze/helper.c
> > +++ b/target/microblaze/helper.c
> > @@ -24,18 +24,7 @@
> >  #include "qemu/host-utils.h"
> >  #include "exec/log.h"
> >  
> > -#if defined(CONFIG_USER_ONLY)
> > -
> > -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> > -                     MMUAccessType access_type, int mmu_idx,
> > -                     bool probe, uintptr_t retaddr)
> > -{
> > -    cs->exception_index = 0xaa;
> > -    cpu_loop_exit_restore(cs, retaddr);
> > -}
> > -
> > -#else /* !CONFIG_USER_ONLY */
> > -
> > +#ifndef CONFIG_USER_ONLY
> >  static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
> >                                      MMUAccessType access_type)
> >  {
> > 
> 
> To the best of my knowledge:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> But I'd feel safer with an Ack-by from Edgar :)


Sorry for the delays!

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



  reply	other threads:[~2021-11-01 16:17 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-30 17:15 [PATCH v6 00/66] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-10-30 17:15 ` [PATCH v6 01/66] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-10-30 17:15 ` [PATCH v6 02/66] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-10-30 17:15 ` [PATCH v6 03/66] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-10-30 17:15 ` [PATCH v6 04/66] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-10-30 17:15 ` [PATCH v6 05/66] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-10-30 17:15 ` [PATCH v6 06/66] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-10-30 17:15 ` [PATCH v6 07/66] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-10-30 17:15 ` [PATCH v6 08/66] linux-user/host/ppc: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 09/66] linux-user/host/alpha: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 10/66] linux-user/host/sparc: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 11/66] linux-user/host/arm: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 12/66] linux-user/host/aarch64: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 13/66] linux-user/host/s390: " Richard Henderson
2021-11-01 16:10   ` Thomas Huth
2021-11-01 17:08     ` Richard Henderson
2021-10-30 17:15 ` [PATCH v6 14/66] linux-user/host/mips: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 15/66] linux-user/host/riscv: " Richard Henderson
2021-10-30 17:15 ` [PATCH v6 16/66] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-10-30 17:15 ` [PATCH v6 17/66] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-10-30 17:15 ` [PATCH v6 18/66] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-10-30 17:15 ` [PATCH v6 19/66] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-10-30 17:15 ` [PATCH v6 20/66] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-10-30 17:15 ` [PATCH v6 21/66] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-10-31 10:26   ` Philippe Mathieu-Daudé
2021-10-30 17:15 ` [PATCH v6 22/66] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-10-30 17:15 ` [PATCH v6 23/66] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-01 16:30   ` Peter Maydell
2021-11-01 17:09     ` Richard Henderson
2021-11-01 17:25       ` Peter Maydell
2021-11-01 17:30         ` Richard Henderson
2021-10-30 17:15 ` [PATCH v6 24/66] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:15 ` [PATCH v6 25/66] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-10-30 17:15 ` [PATCH v6 26/66] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-10-31 10:13   ` Philippe Mathieu-Daudé
2021-10-30 17:15 ` [PATCH v6 27/66] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-10-30 17:15 ` [PATCH v6 28/66] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:15 ` [PATCH v6 29/66] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-10-31 10:14   ` Philippe Mathieu-Daudé
2021-11-01 16:16     ` Edgar E. Iglesias [this message]
2021-10-30 17:15 ` [PATCH v6 30/66] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 31/66] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-10-30 17:16 ` [PATCH v6 32/66] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-10-31 10:11   ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 33/66] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 34/66] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-10-30 17:16 ` [PATCH v6 35/66] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 36/66] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-10-31 10:20   ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 37/66] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-10-30 17:16 ` [PATCH v6 38/66] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-10-31 10:21   ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 39/66] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 40/66] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 41/66] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-10-30 17:16 ` [PATCH v6 42/66] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 43/66] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 44/66] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 45/66] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-01 16:32   ` Peter Maydell
2021-10-30 17:16 ` [PATCH v6 46/66] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-10-31 10:10   ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 47/66] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 48/66] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-10-30 17:16 ` [PATCH v6 49/66] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-10-30 17:16 ` [PATCH v6 50/66] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-10-30 17:16 ` [PATCH v6 51/66] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-10-31 10:15   ` Philippe Mathieu-Daudé
2021-10-30 17:16 ` [PATCH v6 52/66] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 53/66] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-10-30 17:16 ` [PATCH v6 54/66] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-10-30 17:16 ` [PATCH v6 55/66] target/sparc: Split out build_sfsr Richard Henderson
2021-10-30 17:16 ` [PATCH v6 56/66] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-10-30 17:16 ` [PATCH v6 57/66] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-10-30 17:16 ` [PATCH v6 58/66] accel/tcg: Report unaligned load/store " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 59/66] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 60/66] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
2021-10-30 17:16 ` [PATCH v6 61/66] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-10-30 17:16 ` [PATCH v6 62/66] linux-user: Disable more prctl subcodes Richard Henderson
2021-10-30 17:16 ` [PATCH v6 63/66] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
2021-10-30 17:16 ` [PATCH v6 64/66] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-10-30 17:16 ` [PATCH v6 65/66] target/hppa: " Richard Henderson
2021-10-30 17:16 ` [PATCH v6 66/66] target/sh4: " Richard Henderson
2021-10-31 10:30 ` [PATCH v6 00/66] user-only: Cleanup SIGSEGV and SIGBUS handling Philippe Mathieu-Daudé
2021-10-31 13:04   ` Richard Henderson

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