From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Warner Losh" <imp@bsdimp.com>
Subject: [PATCH v7 01/60] accel/tcg: Split out adjust_signal_pc
Date: Mon, 1 Nov 2021 13:26:30 -0400 [thread overview]
Message-ID: <20211101172729.23149-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211101172729.23149-1-richard.henderson@linaro.org>
Split out a function to adjust the raw signal pc into a
value that could be passed to cpu_restore_state.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Adjust pc in place; return MMUAccessType.
---
include/exec/exec-all.h | 10 ++++++++++
accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++----------------
2 files changed, 35 insertions(+), 16 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9d5987ba04..e54f8e5d65 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,
return addr;
}
+/**
+ * adjust_signal_pc:
+ * @pc: raw pc from the host signal ucontext_t.
+ * @is_write: host memory operation was write, or read-modify-write.
+ *
+ * Alter @pc as required for unwinding. Return the type of the
+ * guest memory access -- host reads may be for guest execution.
+ */
+MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
+
/**
* cpu_signal_handler
* @signum: host signal number
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index e6bb29b42d..c02d509ec6 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu,
cpu_loop_exit_noexc(cpu);
}
-/* 'pc' is the host PC at which the exception was raised. 'address' is
- the effective address of the memory exception. 'is_write' is 1 if a
- write caused the exception and otherwise 0'. 'old_set' is the
- signal set which should be restored */
-static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
- int is_write, sigset_t *old_set)
+/*
+ * Adjust the pc to pass to cpu_restore_state; return the memop type.
+ */
+MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
{
- CPUState *cpu = current_cpu;
- CPUClass *cc;
- unsigned long address = (unsigned long)info->si_addr;
- MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
-
switch (helper_retaddr) {
default:
/*
@@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
* pointer into the generated code that will unwind to the
* correct guest pc.
*/
- pc = helper_retaddr;
+ *pc = helper_retaddr;
break;
case 0:
@@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
* Therefore, adjust to compensate for what will be done later
* by cpu_restore_state_from_tb.
*/
- pc += GETPC_ADJ;
+ *pc += GETPC_ADJ;
break;
case 1:
@@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
*
* Like tb_gen_code, release the memory lock before cpu_loop_exit.
*/
- pc = 0;
- access_type = MMU_INST_FETCH;
mmap_unlock();
- break;
+ *pc = 0;
+ return MMU_INST_FETCH;
}
+ return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
+}
+
+/*
+ * 'pc' is the host PC at which the exception was raised.
+ * 'address' is the effective address of the memory exception.
+ * 'is_write' is 1 if a write caused the exception and otherwise 0.
+ * 'old_set' is the signal set which should be restored.
+ */
+static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
+ int is_write, sigset_t *old_set)
+{
+ CPUState *cpu = current_cpu;
+ CPUClass *cc;
+ unsigned long address = (unsigned long)info->si_addr;
+ MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
+
/* For synchronous signals we expect to be coming from the vCPU
* thread (so current_cpu should be valid) and either from running
* code or during translation which can fault as we cross pages.
--
2.25.1
next prev parent reply other threads:[~2021-11-01 17:30 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 17:26 [PATCH v7 00/60] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-11-01 17:26 ` Richard Henderson [this message]
2021-11-01 17:26 ` [PATCH v7 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-11-01 17:26 ` [PATCH v7 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-11-01 17:26 ` [PATCH v7 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-11-01 17:26 ` [PATCH v7 05/60] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-11-01 17:26 ` [PATCH v7 06/60] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-11-01 17:26 ` [PATCH v7 07/60] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-11-01 17:26 ` [PATCH v7 08/60] linux-user/host/ppc: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 09/60] linux-user/host/alpha: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 10/60] linux-user/host/sparc: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 11/60] linux-user/host/arm: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 12/60] linux-user/host/aarch64: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 13/60] linux-user/host/s390: " Richard Henderson
2021-11-02 6:52 ` Thomas Huth
2021-11-01 17:26 ` [PATCH v7 14/60] linux-user/host/mips: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 15/60] linux-user/host/riscv: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 16/60] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-11-01 17:26 ` [PATCH v7 17/60] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-11-01 17:26 ` [PATCH v7 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-11-01 17:26 ` [PATCH v7 19/60] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 20/60] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 21/60] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-11-01 17:26 ` [PATCH v7 23/60] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-11-01 17:26 ` [PATCH v7 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 27/60] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 29/60] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 30/60] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-11-01 17:27 ` [PATCH v7 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 36/60] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 37/60] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 39/60] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 40/60] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-11-01 17:27 ` [PATCH v7 42/60] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 43/60] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 44/60] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 45/60] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-11-01 17:27 ` [PATCH v7 47/60] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-11-01 17:27 ` [PATCH v7 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-11-01 17:27 ` [PATCH v7 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-11-01 17:27 ` [PATCH v7 52/60] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 54/60] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-11-01 17:27 ` [PATCH v7 55/60] target/sparc: Split out build_sfsr Richard Henderson
2021-11-01 17:27 ` [PATCH v7 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 57/60] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 58/60] accel/tcg: Report unaligned load/store " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 59/60] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211101172729.23149-2-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=f4bug@amsat.org \
--cc=imp@bsdimp.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).