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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v7 20/60] linux-user: Add cpu_loop_exit_sigsegv
Date: Mon,  1 Nov 2021 13:26:49 -0400	[thread overview]
Message-ID: <20211101172729.23149-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211101172729.23149-1-richard.henderson@linaro.org>

This is a new interface to be provided by the os emulator for
raising SIGSEGV on fault.  Use the new record_sigsegv target hook.

Reviewed by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/exec-all.h | 15 +++++++++++++++
 accel/tcg/user-exec.c   | 33 ++++++++++++++++++---------------
 linux-user/signal.c     | 30 ++++++++++++++++++++++--------
 3 files changed, 55 insertions(+), 23 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 5dd663c153..f74578500c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
                                  uintptr_t host_pc, abi_ptr guest_addr);
 
+/**
+ * cpu_loop_exit_sigsegv:
+ * @cpu: the cpu context
+ * @addr: the guest address of the fault
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * Use the TCGCPUOps hook to record cpu state, do guest operating system
+ * specific things to raise SIGSEGV, and jump to the main cpu loop.
+ */
+void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
+                                         MMUAccessType access_type,
+                                         bool maperr, uintptr_t ra);
+
 #else
 static inline void mmap_lock(void) {}
 static inline void mmap_unlock(void) {}
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index a0cba61e83..c4f69908e9 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -141,35 +141,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
                                  int fault_size, MMUAccessType access_type,
                                  bool nonfault, uintptr_t ra)
 {
-    int flags;
+    int acc_flag;
+    bool maperr;
 
     switch (access_type) {
     case MMU_DATA_STORE:
-        flags = PAGE_WRITE;
+        acc_flag = PAGE_WRITE_ORG;
         break;
     case MMU_DATA_LOAD:
-        flags = PAGE_READ;
+        acc_flag = PAGE_READ;
         break;
     case MMU_INST_FETCH:
-        flags = PAGE_EXEC;
+        acc_flag = PAGE_EXEC;
         break;
     default:
         g_assert_not_reached();
     }
 
-    if (!guest_addr_valid_untagged(addr) ||
-        page_check_range(addr, 1, flags) < 0) {
-        if (nonfault) {
-            return TLB_INVALID_MASK;
-        } else {
-            CPUState *cpu = env_cpu(env);
-            CPUClass *cc = CPU_GET_CLASS(cpu);
-            cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type,
-                                  MMU_USER_IDX, false, ra);
-            g_assert_not_reached();
+    if (guest_addr_valid_untagged(addr)) {
+        int page_flags = page_get_flags(addr);
+        if (page_flags & acc_flag) {
+            return 0; /* success */
         }
+        maperr = !(page_flags & PAGE_VALID);
+    } else {
+        maperr = true;
     }
-    return 0;
+
+    if (nonfault) {
+        return TLB_INVALID_MASK;
+    }
+
+    cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra);
 }
 
 int probe_access_flags(CPUArchState *env, target_ulong addr,
diff --git a/linux-user/signal.c b/linux-user/signal.c
index b816678ba5..135983747d 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -688,9 +688,27 @@ void force_sigsegv(int oldsig)
     }
     force_sig(TARGET_SIGSEGV);
 }
-
 #endif
 
+void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
+                           MMUAccessType access_type, bool maperr, uintptr_t ra)
+{
+    const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+
+    if (tcg_ops->record_sigsegv) {
+        tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
+    } else if (tcg_ops->tlb_fill) {
+        tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra);
+        g_assert_not_reached();
+    }
+
+    force_sig_fault(TARGET_SIGSEGV,
+                    maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR,
+                    addr);
+    cpu->exception_index = EXCP_INTERRUPT;
+    cpu_loop_exit_restore(cpu, ra);
+}
+
 /* abort execution with signal */
 static void QEMU_NORETURN dump_core_and_abort(int target_sig)
 {
@@ -806,7 +824,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
         access_type = adjust_signal_pc(&pc, is_write);
 
         if (host_sig == SIGSEGV) {
-            const struct TCGCPUOps *tcg_ops;
+            bool maperr = true;
 
             if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) {
                 /* If this was a write to a TB protected page, restart. */
@@ -821,18 +839,14 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
                  * which means that we may get ACCERR when we want MAPERR.
                  */
                 if (page_get_flags(guest_addr) & PAGE_VALID) {
-                    /* maperr = false; */
+                    maperr = false;
                 } else {
                     info->si_code = SEGV_MAPERR;
                 }
             }
 
             sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
-
-            tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
-            tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
-                              MMU_USER_IDX, false, pc);
-            g_assert_not_reached();
+            cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc);
         } else {
             sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
         }
-- 
2.25.1



  parent reply	other threads:[~2021-11-01 17:50 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-01 17:26 [PATCH v7 00/60] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-11-01 17:26 ` [PATCH v7 01/60] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-11-01 17:26 ` [PATCH v7 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-11-01 17:26 ` [PATCH v7 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-11-01 17:26 ` [PATCH v7 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-11-01 17:26 ` [PATCH v7 05/60] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-11-01 17:26 ` [PATCH v7 06/60] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-11-01 17:26 ` [PATCH v7 07/60] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-11-01 17:26 ` [PATCH v7 08/60] linux-user/host/ppc: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 09/60] linux-user/host/alpha: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 10/60] linux-user/host/sparc: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 11/60] linux-user/host/arm: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 12/60] linux-user/host/aarch64: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 13/60] linux-user/host/s390: " Richard Henderson
2021-11-02  6:52   ` Thomas Huth
2021-11-01 17:26 ` [PATCH v7 14/60] linux-user/host/mips: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 15/60] linux-user/host/riscv: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 16/60] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-11-01 17:26 ` [PATCH v7 17/60] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-11-01 17:26 ` [PATCH v7 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-11-01 17:26 ` [PATCH v7 19/60] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-11-01 17:26 ` Richard Henderson [this message]
2021-11-01 17:26 ` [PATCH v7 21/60] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-11-01 17:26 ` [PATCH v7 23/60] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-11-01 17:26 ` [PATCH v7 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 27/60] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 29/60] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 30/60] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-11-01 17:27 ` [PATCH v7 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 36/60] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 37/60] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 39/60] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 40/60] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-11-01 17:27 ` [PATCH v7 42/60] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 43/60] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 44/60] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 45/60] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-11-01 17:27 ` [PATCH v7 47/60] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-11-01 17:27 ` [PATCH v7 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-11-01 17:27 ` [PATCH v7 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-11-01 17:27 ` [PATCH v7 52/60] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 54/60] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-11-01 17:27 ` [PATCH v7 55/60] target/sparc: Split out build_sfsr Richard Henderson
2021-11-01 17:27 ` [PATCH v7 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 57/60] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 58/60] accel/tcg: Report unaligned load/store " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 59/60] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson

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