qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Max Filippov" <jcmvbkbc@gmail.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v7 40/60] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only
Date: Mon,  1 Nov 2021 13:27:09 -0400	[thread overview]
Message-ID: <20211101172729.23149-41-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211101172729.23149-1-richard.henderson@linaro.org>

The fallback code in cpu_loop_exit_sigsegv is sufficient
for xtensa linux-user.

Remove the code from cpu_loop that raised SIGSEGV.

Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/xtensa/cpu.h          |  2 +-
 linux-user/xtensa/cpu_loop.c |  9 ---------
 target/xtensa/cpu.c          |  2 +-
 target/xtensa/helper.c       | 22 +---------------------
 4 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index f9a510ca46..02143f2f77 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -563,10 +563,10 @@ struct XtensaCPU {
 };
 
 
+#ifndef CONFIG_USER_ONLY
 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                          MMUAccessType access_type, int mmu_idx,
                          bool probe, uintptr_t retaddr);
-#ifndef CONFIG_USER_ONLY
 void xtensa_cpu_do_interrupt(CPUState *cpu);
 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c
index 622afbcd34..a83490ab35 100644
--- a/linux-user/xtensa/cpu_loop.c
+++ b/linux-user/xtensa/cpu_loop.c
@@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env)
                 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
                 break;
 
-            case LOAD_PROHIBITED_CAUSE:
-            case STORE_PROHIBITED_CAUSE:
-                info.si_signo = TARGET_SIGSEGV;
-                info.si_errno = 0;
-                info.si_code = TARGET_SEGV_ACCERR;
-                info._sifields._sigfault._addr = env->sregs[EXCVADDR];
-                queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
-                break;
-
             default:
                 fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]);
                 g_assert_not_reached();
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c1cbd03595..224f723236 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
 
 static const struct TCGCPUOps xtensa_tcg_ops = {
     .initialize = xtensa_translate_init,
-    .tlb_fill = xtensa_cpu_tlb_fill,
     .debug_excp_handler = xtensa_breakpoint_handler,
 
 #ifndef CONFIG_USER_ONLY
+    .tlb_fill = xtensa_cpu_tlb_fill,
     .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
     .do_interrupt = xtensa_cpu_do_interrupt,
     .do_transaction_failed = xtensa_cpu_do_transaction_failed,
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f18ab383fd..29d216ec1b 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -242,27 +242,7 @@ void xtensa_cpu_list(void)
     }
 }
 
-#ifdef CONFIG_USER_ONLY
-
-bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                         MMUAccessType access_type, int mmu_idx,
-                         bool probe, uintptr_t retaddr)
-{
-    XtensaCPU *cpu = XTENSA_CPU(cs);
-    CPUXtensaState *env = &cpu->env;
-
-    qemu_log_mask(CPU_LOG_INT,
-                  "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n",
-                  __func__, access_type, address, size);
-    env->sregs[EXCVADDR] = address;
-    env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ?
-                            STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE);
-    cs->exception_index = EXC_USER;
-    cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else /* !CONFIG_USER_ONLY */
-
+#ifndef CONFIG_USER_ONLY
 void xtensa_cpu_do_unaligned_access(CPUState *cs,
                                     vaddr addr, MMUAccessType access_type,
                                     int mmu_idx, uintptr_t retaddr)
-- 
2.25.1



  parent reply	other threads:[~2021-11-01 18:02 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-01 17:26 [PATCH v7 00/60] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-11-01 17:26 ` [PATCH v7 01/60] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-11-01 17:26 ` [PATCH v7 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-11-01 17:26 ` [PATCH v7 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-11-01 17:26 ` [PATCH v7 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-11-01 17:26 ` [PATCH v7 05/60] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-11-01 17:26 ` [PATCH v7 06/60] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-11-01 17:26 ` [PATCH v7 07/60] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-11-01 17:26 ` [PATCH v7 08/60] linux-user/host/ppc: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 09/60] linux-user/host/alpha: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 10/60] linux-user/host/sparc: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 11/60] linux-user/host/arm: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 12/60] linux-user/host/aarch64: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 13/60] linux-user/host/s390: " Richard Henderson
2021-11-02  6:52   ` Thomas Huth
2021-11-01 17:26 ` [PATCH v7 14/60] linux-user/host/mips: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 15/60] linux-user/host/riscv: " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 16/60] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-11-01 17:26 ` [PATCH v7 17/60] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-11-01 17:26 ` [PATCH v7 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-11-01 17:26 ` [PATCH v7 19/60] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 20/60] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 21/60] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-11-01 17:26 ` [PATCH v7 23/60] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-11-01 17:26 ` [PATCH v7 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 27/60] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-11-01 17:26 ` [PATCH v7 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:26 ` [PATCH v7 29/60] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-11-01 17:26 ` [PATCH v7 30/60] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-11-01 17:27 ` [PATCH v7 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 36/60] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 37/60] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-11-01 17:27 ` [PATCH v7 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 39/60] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-11-01 17:27 ` Richard Henderson [this message]
2021-11-01 17:27 ` [PATCH v7 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-11-01 17:27 ` [PATCH v7 42/60] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 43/60] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 44/60] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 45/60] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-11-01 17:27 ` [PATCH v7 47/60] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-11-01 17:27 ` [PATCH v7 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-11-01 17:27 ` [PATCH v7 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-11-01 17:27 ` [PATCH v7 52/60] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 54/60] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-11-01 17:27 ` [PATCH v7 55/60] target/sparc: Split out build_sfsr Richard Henderson
2021-11-01 17:27 ` [PATCH v7 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-11-01 17:27 ` [PATCH v7 57/60] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-11-01 17:27 ` [PATCH v7 58/60] accel/tcg: Report unaligned load/store " Richard Henderson
2021-11-01 17:27 ` [PATCH v7 59/60] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-11-01 17:27 ` [PATCH v7 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211101172729.23149-41-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=f4bug@amsat.org \
    --cc=jcmvbkbc@gmail.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).