From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv
Date: Tue, 2 Nov 2021 07:07:01 -0400 [thread overview]
Message-ID: <20211102110740.215699-22-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org>
Record trap_arg{0,1,2} for the linux-user signal frame.
Fill in the stores to trap_arg{1,2} that were missing
from the previous user-only alpha_cpu_tlb_fill function.
Use maperr to simplify computation of trap_arg1.
Remove the code for EXCP_MMFAULT from cpu_loop, as
that part is now handled by cpu_loop_exit_sigsegv.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.h | 13 +++++++++----
linux-user/alpha/cpu_loop.c | 8 --------
target/alpha/cpu.c | 6 ++++--
target/alpha/helper.c | 39 ++++++++++++++++++++++++++++++++-----
4 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 772828cc26..d49cc36d07 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -439,9 +439,6 @@ void alpha_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
void alpha_cpu_list(void);
-bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
@@ -449,7 +446,15 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
-#ifndef CONFIG_USER_ONLY
+
+#ifdef CONFIG_USER_ONLY
+void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr);
+#else
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c
index 1b00a81385..4cc8e0a55c 100644
--- a/linux-user/alpha/cpu_loop.c
+++ b/linux-user/alpha/cpu_loop.c
@@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env)
fprintf(stderr, "External interrupt. Exit\n");
exit(EXIT_FAILURE);
break;
- case EXCP_MMFAULT:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
- ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
- info._sifields._sigfault._addr = env->trap_arg0;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_UNALIGN:
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 93e16a2ffb..69f32c3078 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,9 +218,11 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
static const struct TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
- .tlb_fill = alpha_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = alpha_cpu_record_sigsegv,
+#else
+ .tlb_fill = alpha_cpu_tlb_fill,
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.do_interrupt = alpha_cpu_do_interrupt,
.do_transaction_failed = alpha_cpu_do_transaction_failed,
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 81550d9e2f..b7e7f73b15 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -120,15 +120,44 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
}
#if defined(CONFIG_USER_ONLY)
-bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
+ target_ulong mmcsr, cause;
- cs->exception_index = EXCP_MMFAULT;
+ /* Assuming !maperr, infer the missing protection. */
+ switch (access_type) {
+ case MMU_DATA_LOAD:
+ mmcsr = MM_K_FOR;
+ cause = 0;
+ break;
+ case MMU_DATA_STORE:
+ mmcsr = MM_K_FOW;
+ cause = 1;
+ break;
+ case MMU_INST_FETCH:
+ mmcsr = MM_K_FOE;
+ cause = -1;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (maperr) {
+ if (address < BIT_ULL(TARGET_VIRT_ADDR_SPACE_BITS - 1)) {
+ /* Userspace address, therefore page not mapped. */
+ mmcsr = MM_K_TNV;
+ } else {
+ /* Kernel or invalid address. */
+ mmcsr = MM_K_ACV;
+ }
+ }
+
+ /* Record the arguments that PALcode would give to the kernel. */
cpu->env.trap_arg0 = address;
- cpu_loop_exit_restore(cs, retaddr);
+ cpu->env.trap_arg1 = mmcsr;
+ cpu->env.trap_arg2 = cause;
}
#else
/* Returns the OSF/1 entMM failure indication, or -1 on success. */
--
2.25.1
next prev parent reply other threads:[~2021-11-02 11:29 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 11:06 [PULL 00/60] accel/tcg patch queue Richard Henderson
2021-11-02 11:06 ` [PULL 01/60] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-11-02 11:06 ` [PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-11-02 11:06 ` [PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-11-02 11:06 ` [PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-11-02 11:06 ` [PULL 05/60] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-11-02 11:06 ` [PULL 06/60] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-11-02 11:06 ` [PULL 07/60] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-11-02 11:06 ` [PULL 08/60] linux-user/host/ppc: " Richard Henderson
2021-11-02 11:06 ` [PULL 09/60] linux-user/host/alpha: " Richard Henderson
2021-11-02 11:06 ` [PULL 10/60] linux-user/host/sparc: " Richard Henderson
2021-11-02 11:06 ` [PULL 11/60] linux-user/host/arm: " Richard Henderson
2021-11-02 11:06 ` [PULL 12/60] linux-user/host/aarch64: " Richard Henderson
2021-11-02 11:06 ` [PULL 13/60] linux-user/host/s390: " Richard Henderson
2021-11-02 11:06 ` [PULL 14/60] linux-user/host/mips: " Richard Henderson
2021-11-02 11:06 ` [PULL 15/60] linux-user/host/riscv: " Richard Henderson
2021-11-02 11:06 ` [PULL 16/60] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-11-02 11:06 ` [PULL 17/60] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-11-02 11:06 ` [PULL 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-11-02 11:06 ` [PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 20/60] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-11-02 11:07 ` Richard Henderson [this message]
2021-11-02 11:07 ` [PULL 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-11-02 11:07 ` [PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-11-02 11:07 ` [PULL 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 27/60] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 30/60] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-11-02 11:07 ` [PULL 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 36/60] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-11-02 11:07 ` [PULL 37/60] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 40/60] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-11-02 11:07 ` [PULL 42/60] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 43/60] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 45/60] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-11-02 11:07 ` [PULL 47/60] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-11-02 11:07 ` [PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-11-02 11:07 ` [PULL 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-11-02 11:07 ` [PULL 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-11-02 11:07 ` [PULL 52/60] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 54/60] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-11-02 11:07 ` [PULL 55/60] target/sparc: Split out build_sfsr Richard Henderson
2021-11-02 11:07 ` [PULL 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 57/60] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-11-02 11:07 ` [PULL 58/60] accel/tcg: Report unaligned load/store " Richard Henderson
2021-11-02 11:07 ` [PULL 59/60] tcg: Add helper_unaligned_{ld,st} for user-only sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
2021-11-02 19:11 ` [PULL 00/60] accel/tcg patch queue Richard Henderson
2021-11-02 23:27 ` Warner Losh
2021-11-02 23:35 ` Richard Henderson
2021-11-02 23:37 ` Warner Losh
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