From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 39/60] target/sparc: Make sparc_cpu_tlb_fill sysemu only
Date: Tue, 2 Nov 2021 07:07:19 -0400 [thread overview]
Message-ID: <20211102110740.215699-40-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211102110740.215699-1-richard.henderson@linaro.org>
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sparc linux-user.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sparc/cpu_loop.c | 25 -------------------------
target/sparc/cpu.c | 2 +-
target/sparc/mmu_helper.c | 25 -------------------------
target/sparc/meson.build | 2 +-
4 files changed, 2 insertions(+), 52 deletions(-)
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
index ad29b4eb6a..0ba65e431c 100644
--- a/linux-user/sparc/cpu_loop.c
+++ b/linux-user/sparc/cpu_loop.c
@@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env)
case TT_WIN_UNF: /* window underflow */
restore_window(env);
break;
- case TT_TFAULT:
- case TT_DFAULT:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->mmuregs[4];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
#else
case TT_SPILL: /* window overflow */
save_window(env);
@@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env)
case TT_FILL: /* window underflow */
restore_window(env);
break;
- case TT_TFAULT:
- case TT_DFAULT:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- if (trapnr == TT_DFAULT)
- info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
- else
- info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
#ifndef TARGET_ABI32
case 0x16e:
flush_windows(env);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 21dd27796d..55268ed2a1 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
static const struct TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
- .tlb_fill = sparc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = sparc_cpu_tlb_fill,
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.do_interrupt = sparc_cpu_do_interrupt,
.do_transaction_failed = sparc_cpu_do_transaction_failed,
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index a44473a1c7..2ad47391d0 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -25,30 +25,6 @@
/* Sparc MMU emulation */
-#if defined(CONFIG_USER_ONLY)
-
-bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
-
- if (access_type == MMU_INST_FETCH) {
- cs->exception_index = TT_TFAULT;
- } else {
- cs->exception_index = TT_DFAULT;
-#ifdef TARGET_SPARC64
- env->dmmu.mmuregs[4] = address;
-#else
- env->mmuregs[4] = address;
-#endif
- }
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else
-
#ifndef TARGET_SPARC64
/*
* Sparc V8 Reference MMU (SRMMU)
@@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return phys_addr;
}
-#endif
diff --git a/target/sparc/meson.build b/target/sparc/meson.build
index a3638b9503..a801802ee2 100644
--- a/target/sparc/meson.build
+++ b/target/sparc/meson.build
@@ -6,7 +6,6 @@ sparc_ss.add(files(
'gdbstub.c',
'helper.c',
'ldst_helper.c',
- 'mmu_helper.c',
'translate.c',
'win_helper.c',
))
@@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helpe
sparc_softmmu_ss = ss.source_set()
sparc_softmmu_ss.add(files(
'machine.c',
+ 'mmu_helper.c',
'monitor.c',
))
--
2.25.1
next prev parent reply other threads:[~2021-11-02 11:37 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 11:06 [PULL 00/60] accel/tcg patch queue Richard Henderson
2021-11-02 11:06 ` [PULL 01/60] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-11-02 11:06 ` [PULL 02/60] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-11-02 11:06 ` [PULL 03/60] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-11-02 11:06 ` [PULL 04/60] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-11-02 11:06 ` [PULL 05/60] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-11-02 11:06 ` [PULL 06/60] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-11-02 11:06 ` [PULL 07/60] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-11-02 11:06 ` [PULL 08/60] linux-user/host/ppc: " Richard Henderson
2021-11-02 11:06 ` [PULL 09/60] linux-user/host/alpha: " Richard Henderson
2021-11-02 11:06 ` [PULL 10/60] linux-user/host/sparc: " Richard Henderson
2021-11-02 11:06 ` [PULL 11/60] linux-user/host/arm: " Richard Henderson
2021-11-02 11:06 ` [PULL 12/60] linux-user/host/aarch64: " Richard Henderson
2021-11-02 11:06 ` [PULL 13/60] linux-user/host/s390: " Richard Henderson
2021-11-02 11:06 ` [PULL 14/60] linux-user/host/mips: " Richard Henderson
2021-11-02 11:06 ` [PULL 15/60] linux-user/host/riscv: " Richard Henderson
2021-11-02 11:06 ` [PULL 16/60] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-11-02 11:06 ` [PULL 17/60] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-11-02 11:06 ` [PULL 18/60] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-11-02 11:06 ` [PULL 19/60] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 20/60] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 21/60] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 22/60] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
2021-11-02 11:07 ` [PULL 23/60] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-11-02 11:07 ` [PULL 26/60] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 27/60] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 28/60] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 29/60] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 30/60] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 31/60] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-11-02 11:07 ` [PULL 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 34/60] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` [PULL 36/60] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-11-02 11:07 ` [PULL 37/60] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-11-02 11:07 ` [PULL 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-11-02 11:07 ` Richard Henderson [this message]
2021-11-02 11:07 ` [PULL 40/60] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-11-02 11:07 ` [PULL 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-11-02 11:07 ` [PULL 42/60] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 43/60] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 44/60] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 45/60] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-11-02 11:07 ` [PULL 47/60] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-11-02 11:07 ` [PULL 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-11-02 11:07 ` [PULL 49/60] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-11-02 11:07 ` [PULL 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-11-02 11:07 ` [PULL 52/60] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 53/60] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 54/60] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-11-02 11:07 ` [PULL 55/60] target/sparc: Split out build_sfsr Richard Henderson
2021-11-02 11:07 ` [PULL 56/60] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-11-02 11:07 ` [PULL 57/60] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-11-02 11:07 ` [PULL 58/60] accel/tcg: Report unaligned load/store " Richard Henderson
2021-11-02 11:07 ` [PULL 59/60] tcg: Add helper_unaligned_{ld,st} for user-only sigbus Richard Henderson
2021-11-02 11:07 ` [PULL 60/60] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
2021-11-02 19:11 ` [PULL 00/60] accel/tcg patch queue Richard Henderson
2021-11-02 23:27 ` Warner Losh
2021-11-02 23:35 ` Richard Henderson
2021-11-02 23:37 ` Warner Losh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211102110740.215699-40-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=f4bug@amsat.org \
--cc=mark.cave-ayland@ilande.co.uk \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).