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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id g10sm3083636wmq.13.2021.11.02.06.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 06:42:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 00/41] MIPS patches for 2021-11-02 Date: Tue, 2 Nov 2021 14:41:59 +0100 Message-Id: <20211102134240.3036524-1-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 844d6dfc3e48a8d404b03ea815868fd01c6f7317= :=0D =0D Merge remote-tracking branch 'remotes/alex.williamson/tags/vfio-update-20= 211101.0' into staging (2021-11-02 07:25:59 -0400)=0D =0D are available in the Git repository at:=0D =0D https://github.com/philmd/qemu.git tags/mips-20211102=0D =0D for you to fetch changes up to 6f08c9c5316a80a049d4861eaac5844466ba3eba:=0D =0D Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" (202= 1-11-02 14:35:22 +0100)=0D =0D ----------------------------------------------------------------=0D MIPS patches queue=0D =0D - Fine-grained MAINTAINERS sections=0D - Fix MSA MADDV.B / MSUBV.B opcodes=0D - Convert MSA opcodes to decodetree=0D - Correct Loongson-3A4000 MSAIR register=0D - Do not accept ELF nanoMIPS binaries on linux-user=0D - Use ISA instead of PCI interrupts in VT82C686 PCI device=0D =0D ----------------------------------------------------------------=0D =0D BALATON Zoltan (4):=0D usb/uhci: Misc clean up=0D usb/uhci: Disallow user creating a vt82c686-uhci-pci device=0D usb/uhci: Replace pci_set_irq with qemu_set_irq=0D hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts=0D =0D Philippe Mathieu-Daud=C3=A9 (37):=0D MAINTAINERS: Add MIPS general architecture support entry=0D MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware=0D MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware=0D target/mips: Fix MSA MADDV.B opcode=0D target/mips: Fix MSA MSUBV.B opcode=0D target/mips: Adjust style in msa_translate_init()=0D target/mips: Use dup_const() to simplify=0D target/mips: Have check_msa_access() return a boolean=0D target/mips: Use enum definitions from CPUMIPSMSADataFormat enum=0D target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v=0D target/mips: Convert MSA LDI opcode to decodetree=0D target/mips: Convert MSA I5 instruction format to decodetree=0D target/mips: Convert MSA BIT instruction format to decodetree=0D target/mips: Convert MSA SHF opcode to decodetree=0D target/mips: Convert MSA I8 instruction format to decodetree=0D target/mips: Convert MSA load/store instruction format to decodetree=0D target/mips: Convert MSA 2RF instruction format to decodetree=0D target/mips: Convert MSA FILL opcode to decodetree=0D target/mips: Convert MSA 2R instruction format to decodetree=0D target/mips: Convert MSA VEC instruction format to decodetree=0D target/mips: Convert MSA 3RF instruction format to decodetree=0D (DF_HALF)=0D target/mips: Convert MSA 3RF instruction format to decodetree=0D (DF_WORD)=0D target/mips: Convert MSA 3R instruction format to decodetree (part=0D 1/4)=0D target/mips: Convert MSA 3R instruction format to decodetree (part=0D 2/4)=0D target/mips: Convert MSA 3R instruction format to decodetree (part=0D 3/4)=0D target/mips: Convert MSA 3R instruction format to decodetree (part=0D 4/4)=0D target/mips: Convert MSA ELM instruction format to decodetree=0D target/mips: Convert MSA COPY_U opcode to decodetree=0D target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree=0D target/mips: Convert MSA MOVE.V opcode to decodetree=0D target/mips: Convert CFCMSA opcode to decodetree=0D target/mips: Convert CTCMSA opcode to decodetree=0D target/mips: Remove generic MSA opcode=0D target/mips: Remove one MSA unnecessary decodetree overlap group=0D target/mips: Fix Loongson-3A4000 MSAIR config register=0D target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU=0D Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"=0D =0D hw/usb/hcd-uhci.h | 3 +-=0D target/mips/tcg/msa.decode | 243 ++-=0D hw/usb/hcd-uhci.c | 14 +-=0D hw/usb/vt82c686-uhci-pci.c | 15 +=0D linux-user/elfload.c | 2 -=0D target/mips/tcg/msa_helper.c | 64 +-=0D target/mips/tcg/msa_translate.c | 2743 +++++++------------------------=0D target/mips/cpu-defs.c.inc | 2 +-=0D MAINTAINERS | 37 +-=0D 9 files changed, 957 insertions(+), 2166 deletions(-)=0D =0D -- =0D 2.31.1=0D =0D