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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id br20sm730408qkb.104.2021.11.02.21.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 21:03:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 00/10] target/arm: Fix insn exception priorities Date: Wed, 3 Nov 2021 00:03:42 -0400 Message-Id: <20211103040352.373688-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Raise pc alignment faults. Fix single-step and pc-align priority over breakpoints. Not yet fixing insn abort priority over breakpoints. r~ Changes for v4: * Rebase on master. * Split some cleanups into new patches. * No special cases in helper_exception_pc_alignment. Changes for v3: * Rebase on siginfo_t patch set -- while probably only force_sig_fault is required, I suspect minor conflicts with the other cleanups. * Typo fix. Changes for v2: * Handle the exceptions in cpu_loop. * Fix how the instruction is raised for aa32 el1. * Add pc alignment test cases. Richard Henderson (10): target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn target/arm: Split arm_pre_translate_insn target/arm: Advance pc for arch single-step exception target/arm: Split compute_fsr_fsc out of arm_deliver_fault target/arm: Take an exception if PC is misaligned target/arm: Assert thumb pc is aligned target/arm: Suppress bp for exceptions with more priority tests/tcg: Add arm and aarch64 pc alignment tests target/arm/helper.h | 1 + target/arm/syndrome.h | 5 +++ linux-user/aarch64/cpu_loop.c | 46 ++++++++++++---------- target/arm/debug_helper.c | 23 +++++++++++ target/arm/gdbstub.c | 9 ++++- target/arm/machine.c | 10 +++++ target/arm/tlb_helper.c | 63 ++++++++++++++++++++++--------- target/arm/translate-a64.c | 23 +++++++++-- target/arm/translate.c | 58 ++++++++++++++++++++-------- tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++ tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 +- tests/tcg/arm/Makefile.target | 4 ++ 13 files changed, 271 insertions(+), 58 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c -- 2.25.1