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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v4 03/10] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
Date: Wed,  3 Nov 2021 00:03:45 -0400	[thread overview]
Message-ID: <20211103040352.373688-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211103040352.373688-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index ead77e9006..a39456ea98 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9629,25 +9629,25 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
     CPUARMState *env = cpu->env_ptr;
+    uint32_t pc = dc->base.pc_next;
     uint32_t insn;
     bool is_16bit;
 
     if (arm_pre_translate_insn(dc)) {
-        dc->base.pc_next += 2;
+        dc->base.pc_next = pc + 2;
         return;
     }
 
-    dc->pc_curr = dc->base.pc_next;
-    insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
+    dc->pc_curr = pc;
+    insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
     is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
-    dc->base.pc_next += 2;
+    pc += 2;
     if (!is_16bit) {
-        uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
-                                       dc->sctlr_b);
-
+        uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
         insn = insn << 16 | insn2;
-        dc->base.pc_next += 2;
+        pc += 2;
     }
+    dc->base.pc_next = pc;
     dc->insn = insn;
 
     if (dc->pstate_il) {
-- 
2.25.1



  parent reply	other threads:[~2021-11-03  4:08 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-03  4:03 [PATCH v4 00/10] target/arm: Fix insn exception priorities Richard Henderson
2021-11-03  4:03 ` [PATCH v4 01/10] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn Richard Henderson
2021-11-05 17:06   ` Peter Maydell
2021-11-03  4:03 ` [PATCH v4 02/10] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn Richard Henderson
2021-11-05 17:06   ` Peter Maydell
2021-11-03  4:03 ` Richard Henderson [this message]
2021-11-05 17:06   ` [PATCH v4 03/10] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn Peter Maydell
2021-11-03  4:03 ` [PATCH v4 04/10] target/arm: Split arm_pre_translate_insn Richard Henderson
2021-11-05 17:06   ` Peter Maydell
2021-11-03  4:03 ` [PATCH v4 05/10] target/arm: Advance pc for arch single-step exception Richard Henderson
2021-11-05 17:07   ` Peter Maydell
2021-11-03  4:03 ` [PATCH v4 06/10] target/arm: Split compute_fsr_fsc out of arm_deliver_fault Richard Henderson
2021-11-05 17:09   ` Peter Maydell
2021-11-03  4:03 ` [PATCH v4 07/10] target/arm: Take an exception if PC is misaligned Richard Henderson
2021-11-05 17:13   ` Peter Maydell
2021-11-03  4:03 ` [PATCH v4 08/10] target/arm: Assert thumb pc is aligned Richard Henderson
2021-11-03  4:03 ` [PATCH v4 09/10] target/arm: Suppress bp for exceptions with more priority Richard Henderson
2021-11-03  4:03 ` [PATCH v4 10/10] tests/tcg: Add arm and aarch64 pc alignment tests Richard Henderson
2021-11-08 14:16 ` [PATCH v4 00/10] target/arm: Fix insn exception priorities Peter Maydell
2021-11-08 14:59   ` Richard Henderson

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