From: Hao Wu <wuhaotsh@google.com>
To: peter.maydell@linaro.org
Cc: richard.henderson@linaro.org, qemu-arm@nongnu.org,
qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com,
Avi.Fishman@nuvoton.com, kfting@nuvoton.com,
hskinnemoen@google.com, f4bug@amsat.org, bin.meng@windriver.com,
qemu-block@nongnu.org, armbru@redhat.com, thuth@redhat.com
Subject: [PATCH v4 3/7] hw/adc: Fix CONV bit in NPCM7XX ADC CON register
Date: Wed, 3 Nov 2021 15:01:29 -0700 [thread overview]
Message-ID: <20211103220133.1422879-1-wuhaotsh@google.com> (raw)
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture<venture@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/adc/npcm7xx_adc.c | 2 +-
tests/qtest/npcm7xx_adc-test.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
index 0f0a9f63e2..47fb9e5f74 100644
--- a/hw/adc/npcm7xx_adc.c
+++ b/hw/adc/npcm7xx_adc.c
@@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4)
#define NPCM7XX_ADC_CON_INT BIT(18)
#define NPCM7XX_ADC_CON_EN BIT(17)
#define NPCM7XX_ADC_CON_RST BIT(16)
-#define NPCM7XX_ADC_CON_CONV BIT(14)
+#define NPCM7XX_ADC_CON_CONV BIT(13)
#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
#define NPCM7XX_ADC_MAX_RESULT 1023
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
index 5ce8ce13b3..aaf127dd42 100644
--- a/tests/qtest/npcm7xx_adc-test.c
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -50,7 +50,7 @@
#define CON_INT BIT(18)
#define CON_EN BIT(17)
#define CON_RST BIT(16)
-#define CON_CONV BIT(14)
+#define CON_CONV BIT(13)
#define CON_DIV(rv) extract32(rv, 1, 8)
#define FST_RDST BIT(1)
--
2.33.1.1089.g2158813163f-goog
next reply other threads:[~2021-11-03 22:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-03 22:01 Hao Wu [this message]
2021-11-03 22:01 ` [PATCH v4 4/7] hw/adc: Make adci[*] R/W in NPCM7XX ADC Hao Wu
2021-11-03 22:01 ` [PATCH v4 5/7] blockdev: Add a new IF type IF_OTHER Hao Wu
2021-11-06 6:47 ` Markus Armbruster
2021-11-03 22:01 ` [PATCH v4 6/7] hw/nvram: Update at24c EEPROM init function in NPCM7xx boards Hao Wu
2021-11-06 6:53 ` Markus Armbruster
2021-11-15 13:19 ` Kevin Wolf
2021-11-15 15:28 ` On configuring onboard block devices with -blockdev (was: [PATCH v4 6/7] hw/nvram: Update at24c EEPROM init function in NPCM7xx boards) Markus Armbruster
2021-11-03 22:01 ` [PATCH v4 7/7] hw/arm: quanta-gbs-bmc add i2c devices Hao Wu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211103220133.1422879-1-wuhaotsh@google.com \
--to=wuhaotsh@google.com \
--cc=Avi.Fishman@nuvoton.com \
--cc=armbru@redhat.com \
--cc=bin.meng@windriver.com \
--cc=f4bug@amsat.org \
--cc=hskinnemoen@google.com \
--cc=kfting@nuvoton.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=thuth@redhat.com \
--cc=venture@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).