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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, clg@kaod.org, danielhb413@gmail.com,
	groug@kaod.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Luis Pires" <luis.pires@eldorado.org.br>,
	qemu-ppc@nongnu.org, "David Gibson" <david@gibson.dropbear.id.au>
Subject: [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] to decodetree
Date: Tue,  9 Nov 2021 16:51:33 +1100	[thread overview]
Message-ID: <20211109055204.230765-24-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20211109055204.230765-1-david@gibson.dropbear.id.au>

From: Luis Pires <luis.pires@eldorado.org.br>

Move the following instructions to decodetree:
dqua:   DFP Quantize
dquaq:  DFP Quantize Quad
drrnd:  DFP Reround
drrndq: DFP Reround Quad

Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-14-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/dfp_helper.c             |  8 ++---
 target/ppc/helper.h                 |  8 ++---
 target/ppc/insn32.decode            | 18 +++++++++--
 target/ppc/translate/dfp-impl.c.inc | 50 +++++++++++++----------------
 target/ppc/translate/dfp-ops.c.inc  | 25 ---------------
 5 files changed, 47 insertions(+), 62 deletions(-)

diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index df3e6c7cb1..a50a73d3c0 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -769,8 +769,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a,        \
     set_dfp##size(t, &dfp.vt);                                          \
 }
 
-DFP_HELPER_QUA(dqua, 64)
-DFP_HELPER_QUA(dquaq, 128)
+DFP_HELPER_QUA(DQUA, 64)
+DFP_HELPER_QUA(DQUAQ, 128)
 
 static void _dfp_reround(uint8_t rmc, int32_t ref_sig, int32_t xmax,
                              struct PPC_DFP *dfp)
@@ -847,8 +847,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a,        \
     set_dfp##size(t, &dfp.vt);                                          \
 }
 
-DFP_HELPER_RRND(drrnd, 64)
-DFP_HELPER_RRND(drrndq, 128)
+DFP_HELPER_RRND(DRRND, 64)
+DFP_HELPER_RRND(DRRNDQ, 128)
 
 #define DFP_HELPER_RINT(op, postprocs, size)                                   \
 void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b,               \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 70bc8ac579..70aebdfeff 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -722,10 +722,10 @@ DEF_HELPER_3(DTSTSFI, i32, env, i32, fprp)
 DEF_HELPER_3(DTSTSFIQ, i32, env, i32, fprp)
 DEF_HELPER_5(DQUAI, void, env, fprp, fprp, i32, i32)
 DEF_HELPER_5(DQUAIQ, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DQUA, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DQUAQ, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DRRND, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DRRNDQ, void, env, fprp, fprp, fprp, i32)
 DEF_HELPER_5(DRINTX, void, env, fprp, fprp, i32, i32)
 DEF_HELPER_5(DRINTXQ, void, env, fprp, fprp, i32, i32)
 DEF_HELPER_5(DRINTN, void, env, fprp, fprp, i32, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 5369af17b6..f7c8d50bd9 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -84,11 +84,19 @@
 %z22_frap       17:4 !function=times_2
 @Z22_bf_frap    ...... bf:3 .. ....0 dm:6 ......... .           &Z22_bf_fra fra=%z22_frap
 
-&Z23_tb         frt frb r:bool rmc rc:bool
-@Z23_tb         ...... frt:5 .... r:1 frb:5 rmc:2 ........ rc:1 &Z23_tb
+&Z23_tab        frt fra frb rmc rc:bool
+@Z23_tab        ...... frt:5 fra:5 frb:5 rmc:2 ........ rc:1    &Z23_tab
 
 %z23_frtp       22:4 !function=times_2
+%z23_frap       17:4 !function=times_2
 %z23_frbp       12:4 !function=times_2
+@Z23_tabp       ...... ....0 ....0 ....0 rmc:2 ........ rc:1    &Z23_tab frt=%z23_frtp fra=%z23_frap frb=%z23_frbp
+
+@Z23_tp_a_bp    ...... ....0 fra:5 ....0 rmc:2 ........ rc:1    &Z23_tab frt=%z23_frtp frb=%z23_frbp
+
+&Z23_tb         frt frb r:bool rmc rc:bool
+@Z23_tb         ...... frt:5 .... r:1 frb:5 rmc:2 ........ rc:1 &Z23_tb
+
 @Z23_tbp        ...... ....0 .... r:1 ....0 rmc:2 ........ rc:1 &Z23_tb frt=%z23_frtp frb=%z23_frbp
 
 &Z23_te_tb      te frt frb rmc rc:bool
@@ -250,6 +258,12 @@ DTSTSFIQ        111111 ... - ...... ..... 1010100011 -  @X_bf_uim_bp
 DQUAI           111011 ..... ..... ..... .. 01000011 .  @Z23_te_tb
 DQUAIQ          111111 ..... ..... ..... .. 01000011 .  @Z23_te_tbp
 
+DQUA            111011 ..... ..... ..... .. 00000011 .  @Z23_tab
+DQUAQ           111111 ..... ..... ..... .. 00000011 .  @Z23_tabp
+
+DRRND           111011 ..... ..... ..... .. 00100011 .  @Z23_tab
+DRRNDQ          111111 ..... ..... ..... .. 00100011 .  @Z23_tp_a_bp
+
 DRINTX          111011 ..... ---- . ..... .. 01100011 . @Z23_tb
 DRINTXQ         111111 ..... ---- . ..... .. 01100011 . @Z23_tbp
 
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index cb481d028a..30d65ffb46 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -86,28 +86,25 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
     return true;                                             \
 }
 
-#define GEN_DFP_T_A_B_I32_Rc(name, i32fld)       \
-static void gen_##name(DisasContext *ctx)        \
-{                                                \
-    TCGv_ptr rt, ra, rb;                         \
-    TCGv_i32 i32;                                \
-    if (unlikely(!ctx->fpu_enabled)) {           \
-        gen_exception(ctx, POWERPC_EXCP_FPU);    \
-        return;                                  \
-    }                                            \
-    rt = gen_fprp_ptr(rD(ctx->opcode));          \
-    ra = gen_fprp_ptr(rA(ctx->opcode));          \
-    rb = gen_fprp_ptr(rB(ctx->opcode));          \
-    i32 = tcg_const_i32(i32fld(ctx->opcode));    \
-    gen_helper_##name(cpu_env, rt, ra, rb, i32); \
-    if (unlikely(Rc(ctx->opcode) != 0)) {        \
-        gen_set_cr1_from_fpscr(ctx);             \
-    }                                            \
-    tcg_temp_free_ptr(rt);                       \
-    tcg_temp_free_ptr(rb);                       \
-    tcg_temp_free_ptr(ra);                       \
-    tcg_temp_free_i32(i32);                      \
-    }
+#define TRANS_DFP_T_A_B_I32_Rc(NAME, I32FLD)                 \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a)   \
+{                                                            \
+    TCGv_ptr rt, ra, rb;                                     \
+    REQUIRE_INSNS_FLAGS2(ctx, DFP);                          \
+    REQUIRE_FPU(ctx);                                        \
+    rt = gen_fprp_ptr(a->frt);                               \
+    ra = gen_fprp_ptr(a->fra);                               \
+    rb = gen_fprp_ptr(a->frb);                               \
+    gen_helper_##NAME(cpu_env, rt, ra, rb,                   \
+                      tcg_constant_i32(a->I32FLD));          \
+    if (unlikely(a->rc)) {                                   \
+        gen_set_cr1_from_fpscr(ctx);                         \
+    }                                                        \
+    tcg_temp_free_ptr(rt);                                   \
+    tcg_temp_free_ptr(ra);                                   \
+    tcg_temp_free_ptr(rb);                                   \
+    return true;                                             \
+}
 
 #define GEN_DFP_T_B_Rc(name)                     \
 static void gen_##name(DisasContext *ctx)        \
@@ -172,10 +169,10 @@ TRANS_DFP_BF_I_B(DTSTSFI)
 TRANS_DFP_BF_I_B(DTSTSFIQ)
 TRANS_DFP_T_B_U32_U32_Rc(DQUAI, te, rmc)
 TRANS_DFP_T_B_U32_U32_Rc(DQUAIQ, te, rmc)
-GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
-GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
-GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
-GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
+TRANS_DFP_T_A_B_I32_Rc(DQUA, rmc)
+TRANS_DFP_T_A_B_I32_Rc(DQUAQ, rmc)
+TRANS_DFP_T_A_B_I32_Rc(DRRND, rmc)
+TRANS_DFP_T_A_B_I32_Rc(DRRNDQ, rmc)
 TRANS_DFP_T_B_U32_U32_Rc(DRINTX, r, rmc)
 TRANS_DFP_T_B_U32_U32_Rc(DRINTXQ, r, rmc)
 TRANS_DFP_T_B_U32_U32_Rc(DRINTN, r, rmc)
@@ -201,7 +198,6 @@ GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
 
-#undef GEN_DFP_T_A_B_I32_Rc
 #undef GEN_DFP_T_B_Rc
 #undef GEN_DFP_T_FPR_I32_Rc
 
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index c563f84a0b..3e0dfae796 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -5,12 +5,6 @@ GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
 
-#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-
 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
 
@@ -18,12 +12,6 @@ GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
 
-#define _GEN_DFP_QUADx4(name, op1, op2, mask)                         \
-GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-
 #define GEN_DFP_T_B_Rc(name, op1, op2) \
 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
 
@@ -36,15 +24,6 @@ _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
 
-#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
-
-#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
-
 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
 
@@ -63,10 +42,6 @@ _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
 
-GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
-GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
-GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
-GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
-- 
2.33.1



  parent reply	other threads:[~2021-11-09  6:56 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09  5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
2021-11-09  5:51 ` [PULL 01/54] target/ppc: introduce do_ea_calc David Gibson
2021-11-09  5:51 ` [PULL 02/54] target/ppc: move resolve_PLS_D to translate.c David Gibson
2021-11-09  5:51 ` [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree David Gibson
2021-11-10 16:33   ` Laurent Vivier
2021-11-10 16:56     ` Cédric Le Goater
2021-11-10 17:04       ` Laurent Vivier
2021-11-12 13:39         ` Cédric Le Goater
2021-11-09  5:51 ` [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions David Gibson
2021-11-09  5:51 ` [PULL 05/54] target/ppc: Move LQ and STQ to decodetree David Gibson
2021-11-09  5:51 ` [PULL 06/54] target/ppc: Implement PLQ and PSTQ David Gibson
2021-11-09  5:51 ` [PULL 07/54] target/ppc: Implement cntlzdm David Gibson
2021-11-09  5:51 ` [PULL 08/54] target/ppc: Implement cnttzdm David Gibson
2021-11-09  5:51 ` [PULL 09/54] target/ppc: Implement pdepd instruction David Gibson
2021-11-09  5:51 ` [PULL 10/54] target/ppc: Implement pextd instruction David Gibson
2021-11-09  5:51 ` [PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128 David Gibson
2021-11-09  5:51 ` [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c David Gibson
2021-11-09  5:51 ` [PULL 13/54] target/ppc: Introduce REQUIRE_FPU David Gibson
2021-11-09  5:51 ` [PULL 14/54] target/ppc: Implement DCFFIXQQ David Gibson
2021-11-09  5:51 ` [PULL 15/54] host-utils: Introduce mulu128 David Gibson
2021-11-09  5:51 ` [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128 David Gibson
2021-11-09  5:51 ` [PULL 17/54] target/ppc: Implement DCTFIXQQ David Gibson
2021-11-09  5:51 ` [PULL 18/54] target/ppc: Do not update nip on DFP instructions David Gibson
2021-11-09  5:51 ` [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree David Gibson
2021-11-09  5:51 ` [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] " David Gibson
2021-11-09  5:51 ` [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] " David Gibson
2021-11-09  5:51 ` [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] " David Gibson
2021-11-09  5:51 ` David Gibson [this message]
2021-11-09  5:51 ` [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] " David Gibson
2021-11-09  5:51 ` [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] " David Gibson
2021-11-09  5:51 ` [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents David Gibson
2021-11-09  5:51 ` [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled David Gibson
2021-11-09  5:51 ` [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc David Gibson
2021-11-09  5:51 ` [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions David Gibson
2021-11-09  5:51 ` [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction David Gibson
2021-11-09  5:51 ` [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions David Gibson
2021-11-09  5:51 ` [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns David Gibson
2021-11-09  5:51 ` [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns David Gibson
2021-11-09  5:51 ` [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns David Gibson
2021-11-09  5:51 ` [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree David Gibson
2021-11-09  5:51 ` [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns David Gibson
2021-11-09  5:51 ` [PULL 37/54] target/ppc: Introduce REQUIRE_VSX macro David Gibson
2021-11-09  5:51 ` [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr David Gibson
2021-11-09  5:51 ` [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree David Gibson
2021-11-09  5:51 ` [PULL 40/54] target/ppc: moved stxvx and lxvx " David Gibson
2021-11-09  5:51 ` [PULL 41/54] target/ppc: added the instructions LXVP and STXVP David Gibson
2021-11-09  5:51 ` [PULL 42/54] target/ppc: added the instructions LXVPX and STXVPX David Gibson
2021-11-09  5:51 ` [PULL 43/54] target/ppc: added the instructions PLXV and PSTXV David Gibson
2021-11-09  5:51 ` [PULL 44/54] target/ppc: added the instructions PLXVP and PSTXVP David Gibson
2021-11-09  5:51 ` [PULL 45/54] target/ppc: moved XXSPLTW to using decodetree David Gibson
2021-11-09  5:51 ` [PULL 46/54] target/ppc: moved XXSPLTIB " David Gibson
2021-11-09  5:51 ` [PULL 47/54] target/ppc: implemented XXSPLTI32DX David Gibson
2021-11-09  5:51 ` [PULL 48/54] target/ppc: Implemented XXSPLTIW using decodetree David Gibson
2021-11-09  5:51 ` [PULL 49/54] target/ppc: implemented XXSPLTIDP instruction David Gibson
2021-11-09  5:52 ` [PULL 50/54] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions David Gibson
2021-11-09  5:52 ` [PULL 51/54] target/ppc: Implement lxvkq instruction David Gibson
2021-11-09  5:52 ` [PULL 52/54] target/ppc: cntlzdm/cnttzdm implementation without brcond David Gibson
2021-11-09  5:52 ` [PULL 53/54] target/ppc, hw/ppc: Change maintainers David Gibson
2021-11-09  5:52 ` [PULL 54/54] spapr_numa.c: FORM2 table handle nodes with no distance info David Gibson
2021-11-09  8:41 ` [PULL 00/54] ppc-for-6.2 queue 20211109 Richard Henderson

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