* [PULL 01/54] target/ppc: introduce do_ea_calc
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 02/54] target/ppc: move resolve_PLS_D to translate.c David Gibson
` (53 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel, qemu-ppc,
Matheus Ferst, David Gibson
From: Fernando Eckhardt Valle <phervalle@gmail.com>
The do_ea_calc function will calculate the effective address(EA)
according to PowerIsa 3.1. With that, it was replaced part of
do_ldst() that calculates the EA by this new function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle (pherde) <phervalle@gmail.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-2-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 14 ++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 10 +---------
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 518337bcb7..b3264aab58 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3197,6 +3197,20 @@ static inline void gen_align_no_le(DisasContext *ctx)
(ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
}
+static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
+{
+ TCGv ea = tcg_temp_new();
+ if (ra) {
+ tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
+ } else {
+ tcg_gen_mov_tl(ea, displ);
+ }
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(ea, ea);
+ }
+ return ea;
+}
+
/*** Integer load ***/
#define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
#define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 2e2518ee15..caef5d89cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -51,15 +51,7 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
}
gen_set_access_type(ctx, ACCESS_INT);
- ea = tcg_temp_new();
- if (ra) {
- tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
- } else {
- tcg_gen_mov_tl(ea, displ);
- }
- if (NARROW_MODE(ctx)) {
- tcg_gen_ext32u_tl(ea, ea);
- }
+ ea = do_ea_calc(ctx, ra, displ);
mop ^= ctx->default_tcg_memop_mask;
if (store) {
tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 02/54] target/ppc: move resolve_PLS_D to translate.c
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
2021-11-09 5:51 ` [PULL 01/54] target/ppc: introduce do_ea_calc David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree David Gibson
` (52 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel, qemu-ppc,
Matheus Ferst, David Gibson
From: Fernando Eckhardt Valle <phervalle@gmail.com>
Move resolve_PLS_D from fixedpoint-impl.c.inc to translate.c
because this way the function can be used not only by fixed
point instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <phervalle@gmail.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-3-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 19 +++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 19 -------------------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b3264aab58..3f50f44c19 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7502,6 +7502,25 @@ static int times_4(DisasContext *ctx, int x)
#include "decode-insn64.c.inc"
#include "power8-pmu-regs.c.inc"
+/*
+ * Incorporate CIA into the constant when R=1.
+ * Validate that when R=1, RA=0.
+ */
+static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
+{
+ d->rt = a->rt;
+ d->ra = a->ra;
+ d->si = a->si;
+ if (a->r) {
+ if (unlikely(a->ra != 0)) {
+ gen_invalid(ctx);
+ return false;
+ }
+ d->si += ctx->cia;
+ }
+ return true;
+}
+
#include "translate/fixedpoint-impl.c.inc"
#include "translate/fp-impl.c.inc"
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index caef5d89cd..812b7ddd0a 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -17,25 +17,6 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-/*
- * Incorporate CIA into the constant when R=1.
- * Validate that when R=1, RA=0.
- */
-static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
-{
- d->rt = a->rt;
- d->ra = a->ra;
- d->si = a->si;
- if (a->r) {
- if (unlikely(a->ra != 0)) {
- gen_invalid(ctx);
- return false;
- }
- d->si += ctx->cia;
- }
- return true;
-}
-
/*
* Fixed-Point Load/Store Instructions
*/
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
2021-11-09 5:51 ` [PULL 01/54] target/ppc: introduce do_ea_calc David Gibson
2021-11-09 5:51 ` [PULL 02/54] target/ppc: move resolve_PLS_D to translate.c David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-10 16:33 ` Laurent Vivier
2021-11-09 5:51 ` [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions David Gibson
` (51 subsequent siblings)
54 siblings, 1 reply; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel,
Fernando Eckhardt Valle, qemu-ppc, Matheus Ferst, David Gibson
From: Fernando Eckhardt Valle <phervalle@gmail.com>
Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
stfdux) from legacy system to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 24 +++
target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
target/ppc/translate/fp-ops.c.inc | 29 ----
3 files changed, 95 insertions(+), 205 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9fd8d6b817..19ef9bff67 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -114,6 +114,30 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
+### Float-Point Load Instructions
+
+LFS 110000 ..... ..... ................ @D
+LFSU 110001 ..... ..... ................ @D
+LFSX 011111 ..... ..... ..... 1000010111 - @X
+LFSUX 011111 ..... ..... ..... 1000110111 - @X
+
+LFD 110010 ..... ..... ................ @D
+LFDU 110011 ..... ..... ................ @D
+LFDX 011111 ..... ..... ..... 1001010111 - @X
+LFDUX 011111 ..... ..... ..... 1001110111 - @X
+
+### Float-Point Store Instructions
+
+STFS 110100 ..... ...... ............... @D
+STFSU 110101 ..... ...... ............... @D
+STFSX 011111 ..... ...... .... 1010010111 - @X
+STFSUX 011111 ..... ...... .... 1010110111 - @X
+
+STFD 110110 ..... ...... ............... @D
+STFDU 110111 ..... ...... ............... @D
+STFDX 011111 ..... ...... .... 1011010111 - @X
+STFDUX 011111 ..... ...... .... 1011110111 - @X
+
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 9f7868ee28..57a799db1c 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -854,99 +854,6 @@ static void gen_mtfsfi(DisasContext *ctx)
gen_helper_float_check_status(cpu_env);
}
-/*** Floating-point load ***/
-#define GEN_LDF(name, ldop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDUF(name, ldop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDUXF(name, ldop, opc, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- t0 = tcg_temp_new_i64(); \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDXF(name, ldop, opc2, opc3, type) \
-static void glue(gen_, name##x)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, t0, EA); \
- set_fpr(rD(ctx->opcode), t0); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_LDFS(name, ldop, op, type) \
-GEN_LDF(name, ldop, op | 0x20, type); \
-GEN_LDUF(name, ldop, op | 0x21, type); \
-GEN_LDUXF(name, ldop, op | 0x01, type); \
-GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-
static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@@ -955,11 +862,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
tcg_temp_free_i32(tmp);
}
- /* lfd lfdu lfdux lfdx */
-GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
- /* lfs lfsu lfsux lfsx */
-GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
-
/* lfdepx (external PID lfdx) */
static void gen_lfdepx(DisasContext *ctx)
{
@@ -1089,73 +991,6 @@ static void gen_lfiwzx(DisasContext *ctx)
tcg_temp_free(EA);
tcg_temp_free_i64(t0);
}
-/*** Floating-point store ***/
-#define GEN_STF(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STUF(name, stop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_imm_index(ctx, EA, 0); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
-
-#define GEN_STUXF(name, stop, opc, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 t0; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_FLOAT); \
- EA = tcg_temp_new(); \
- t0 = tcg_temp_new_i64(); \
- gen_addr_reg_index(ctx, EA); \
- get_fpr(t0, rS(ctx->opcode)); \
- gen_qemu_##stop(ctx, t0, EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(t0); \
-}
#define GEN_STXF(name, stop, opc2, opc3, type) \
static void glue(gen_, name##x)(DisasContext *ctx) \
@@ -1176,12 +1011,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
tcg_temp_free_i64(t0); \
}
-#define GEN_STFS(name, stop, op, type) \
-GEN_STF(name, stop, op | 0x20, type); \
-GEN_STUF(name, stop, op | 0x21, type); \
-GEN_STUXF(name, stop, op | 0x01, type); \
-GEN_STXF(name, stop, 0x17, op | 0x00, type)
-
static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@@ -1190,11 +1019,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
tcg_temp_free_i32(tmp);
}
-/* stfd stfdu stfdux stfdx */
-GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT);
-/* stfs stfsu stfsux stfsx */
-GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
-
/* stfdepx (external PID lfdx) */
static void gen_stfdepx(DisasContext *ctx)
{
@@ -1473,6 +1297,77 @@ static void gen_stfqx(DisasContext *ctx)
tcg_temp_free_i64(t1);
}
+/* Floating-point Load/Store Instructions */
+static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
+ bool update, bool store, bool single)
+{
+ TCGv ea;
+ TCGv_i64 t0;
+ REQUIRE_INSNS_FLAGS(ctx, FLOAT);
+ REQUIRE_FPU(ctx);
+ if (update && ra == 0) {
+ gen_invalid(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_FLOAT);
+ t0 = tcg_temp_new_i64();
+ ea = do_ea_calc(ctx, ra, displ);
+ if (store) {
+ get_fpr(t0, rt);
+ if (single) {
+ gen_qemu_st32fs(ctx, t0, ea);
+ } else {
+ gen_qemu_st64_i64(ctx, t0, ea);
+ }
+ } else {
+ if (single) {
+ gen_qemu_ld32fs(ctx, t0, ea);
+ } else {
+ gen_qemu_ld64_i64(ctx, t0, ea);
+ }
+ set_fpr(rt, t0);
+ }
+ if (update) {
+ tcg_gen_mov_tl(cpu_gpr[rt], ea);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free(ea);
+ return true;
+}
+
+static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
+ bool single)
+{
+ return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store,
+ single);
+}
+
+static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
+ bool store, bool single)
+{
+ return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
+}
+
+TRANS(LFS, do_lsfp_D, false, false, true)
+TRANS(LFSU, do_lsfp_D, true, false, true)
+TRANS(LFSX, do_lsfp_X, false, false, true)
+TRANS(LFSUX, do_lsfp_X, true, false, true)
+
+TRANS(LFD, do_lsfp_D, false, false, false)
+TRANS(LFDU, do_lsfp_D, true, false, false)
+TRANS(LFDX, do_lsfp_X, false, false, false)
+TRANS(LFDUX, do_lsfp_X, true, false, false)
+
+TRANS(STFS, do_lsfp_D, false, true, true)
+TRANS(STFSU, do_lsfp_D, true, true, true)
+TRANS(STFSX, do_lsfp_X, false, true, true)
+TRANS(STFSUX, do_lsfp_X, true, true, true)
+
+TRANS(STFD, do_lsfp_D, false, true, false)
+TRANS(STFDU, do_lsfp_D, true, true, false)
+TRANS(STFDX, do_lsfp_X, false, true, false)
+TRANS(STFDUX, do_lsfp_X, true, true, false)
+
#undef _GEN_FLOAT_ACB
#undef GEN_FLOAT_ACB
#undef _GEN_FLOAT_AB
diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
index 88fab65628..4260635a12 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -50,43 +50,14 @@ GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
-#define GEN_LDF(name, ldop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUF(name, ldop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUXF(name, ldop, opc, type) \
-GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
-#define GEN_LDXF(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_LDFS(name, ldop, op, type) \
-GEN_LDF(name, ldop, op | 0x20, type) \
-GEN_LDUF(name, ldop, op | 0x21, type) \
-GEN_LDUXF(name, ldop, op | 0x01, type) \
-GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-
-GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
-GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
-#define GEN_STF(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUF(name, stop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUXF(name, stop, opc, type) \
-GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
#define GEN_STXF(name, stop, opc2, opc3, type) \
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
-#define GEN_STFS(name, stop, op, type) \
-GEN_STF(name, stop, op | 0x20, type) \
-GEN_STUF(name, stop, op | 0x21, type) \
-GEN_STUXF(name, stop, op | 0x01, type) \
-GEN_STXF(name, stop, 0x17, op | 0x00, type)
-GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
-GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree
2021-11-09 5:51 ` [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree David Gibson
@ 2021-11-10 16:33 ` Laurent Vivier
2021-11-10 16:56 ` Cédric Le Goater
0 siblings, 1 reply; 60+ messages in thread
From: Laurent Vivier @ 2021-11-10 16:33 UTC (permalink / raw)
To: David Gibson, peter.maydell, clg, danielhb413, groug,
Mark Cave-Ayland
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel,
Fernando Eckhardt Valle, qemu-ppc, Matheus Ferst
On 09/11/2021 06:51, David Gibson wrote:
> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>
> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
> and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
> stfdux) from legacy system to decodetree.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/insn32.decode | 24 +++
> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
> target/ppc/translate/fp-ops.c.inc | 29 ----
> 3 files changed, 95 insertions(+), 205 deletions(-)
>
This patch breaks qemu linux-user with an ubuntu bionic chroot.
The fix proposed by Matheus [1] fixes it for me.
When will it be merged?
It's needed in 6.2
Thanks,
Laurent
[1]
https://patchew.org/QEMU/20211029202424.175401-1-matheus.ferst@eldorado.org.br/20211029202424.175401-4-matheus.ferst@eldorado.org.br/#c799859a-4fdc-9d69-7a87-5e69cee15ef3@eldorado.org.br
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index d1dbb1b96b..c9e05201d9 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -1328,7 +1328,7 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ,
set_fpr(rt, t0);
}
if (update) {
- tcg_gen_mov_tl(cpu_gpr[rt], ea);
+ tcg_gen_mov_tl(cpu_gpr[ra], ea);
}
tcg_temp_free_i64(t0);
tcg_temp_free(ea);
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree
2021-11-10 16:33 ` Laurent Vivier
@ 2021-11-10 16:56 ` Cédric Le Goater
2021-11-10 17:04 ` Laurent Vivier
0 siblings, 1 reply; 60+ messages in thread
From: Cédric Le Goater @ 2021-11-10 16:56 UTC (permalink / raw)
To: Laurent Vivier, David Gibson, peter.maydell, danielhb413, groug,
Mark Cave-Ayland
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel,
Fernando Eckhardt Valle, qemu-ppc, Matheus Ferst
On 11/10/21 17:33, Laurent Vivier wrote:
> On 09/11/2021 06:51, David Gibson wrote:
>> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>>
>> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
>> and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
>> stfdux) from legacy system to decodetree.
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br>
>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>> target/ppc/insn32.decode | 24 +++
>> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
>> target/ppc/translate/fp-ops.c.inc | 29 ----
>> 3 files changed, 95 insertions(+), 205 deletions(-)
>>
>
> This patch breaks qemu linux-user with an ubuntu bionic chroot.
>
> The fix proposed by Matheus [1] fixes it for me.
> When will it be merged?
> It's needed in 6.2
It's queued for 6.2 :
https://github.com/legoater/qemu/commits/ppc-6.2
I wanted to wait the end of the week before sending a PR. Unless
this is critical for you of course.
Thanks,
C.
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree
2021-11-10 16:56 ` Cédric Le Goater
@ 2021-11-10 17:04 ` Laurent Vivier
2021-11-12 13:39 ` Cédric Le Goater
0 siblings, 1 reply; 60+ messages in thread
From: Laurent Vivier @ 2021-11-10 17:04 UTC (permalink / raw)
To: Cédric Le Goater, David Gibson, peter.maydell, danielhb413,
groug, Mark Cave-Ayland
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel,
Fernando Eckhardt Valle, qemu-ppc, Matheus Ferst
On 10/11/2021 17:56, Cédric Le Goater wrote:
> On 11/10/21 17:33, Laurent Vivier wrote:
>> On 09/11/2021 06:51, David Gibson wrote:
>>> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>>>
>>> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
>>> and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
>>> stfdux) from legacy system to decodetree.
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
>>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>>> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br>
>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>>> ---
>>> target/ppc/insn32.decode | 24 +++
>>> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
>>> target/ppc/translate/fp-ops.c.inc | 29 ----
>>> 3 files changed, 95 insertions(+), 205 deletions(-)
>>>
>>
>> This patch breaks qemu linux-user with an ubuntu bionic chroot.
>>
>> The fix proposed by Matheus [1] fixes it for me.
>> When will it be merged?
>> It's needed in 6.2
>
>
> It's queued for 6.2 :
>
> https://github.com/legoater/qemu/commits/ppc-6.2
>
> I wanted to wait the end of the week before sending a PR. Unless
> this is critical for you of course.
Not it's not critical. It can wait the end of the week.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree
2021-11-10 17:04 ` Laurent Vivier
@ 2021-11-12 13:39 ` Cédric Le Goater
0 siblings, 0 replies; 60+ messages in thread
From: Cédric Le Goater @ 2021-11-12 13:39 UTC (permalink / raw)
To: Laurent Vivier, David Gibson, peter.maydell, danielhb413, groug,
Mark Cave-Ayland
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel,
Fernando Eckhardt Valle, qemu-ppc, Matheus Ferst
On 11/10/21 18:04, Laurent Vivier wrote:
> On 10/11/2021 17:56, Cédric Le Goater wrote:
>> On 11/10/21 17:33, Laurent Vivier wrote:
>>> On 09/11/2021 06:51, David Gibson wrote:
>>>> From: Fernando Eckhardt Valle <phervalle@gmail.com>
>>>>
>>>> Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
>>>> and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
>>>> stfdux) from legacy system to decodetree.
>>>>
>>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>> Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
>>>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>>>> Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br>
>>>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>>>> ---
>>>> target/ppc/insn32.decode | 24 +++
>>>> target/ppc/translate/fp-impl.c.inc | 247 +++++++++--------------------
>>>> target/ppc/translate/fp-ops.c.inc | 29 ----
>>>> 3 files changed, 95 insertions(+), 205 deletions(-)
>>>>
>>>
>>> This patch breaks qemu linux-user with an ubuntu bionic chroot.
>>>
>>> The fix proposed by Matheus [1] fixes it for me.
>>> When will it be merged?
>>> It's needed in 6.2
>>
>>
>> It's queued for 6.2 :
>>
>> https://github.com/legoater/qemu/commits/ppc-6.2
>>
>> I wanted to wait the end of the week before sending a PR. Unless
>> this is critical for you of course.
>
> Not it's not critical. It can wait the end of the week.
It's merged.
Thanks,
C.
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (2 preceding siblings ...)
2021-11-09 5:51 ` [PULL 03/54] target/ppc: Move load and store floating point instructions to decodetree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 05/54] target/ppc: Move LQ and STQ to decodetree David Gibson
` (50 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Fernando Eckhardt Valle, Richard Henderson, qemu-devel,
Fernando Eckhardt Valle, qemu-ppc, Matheus Ferst, David Gibson
From: Fernando Eckhardt Valle <phervalle@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-5-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 11 +++++++++++
target/ppc/translate/fp-impl.c.inc | 14 ++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 72c5944a53..11e5ea81d6 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -56,6 +56,17 @@ PSTD 000001 00 0--.-- .................. \
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
+### Float-Point Load and Store Instructions
+
+PLFS 000001 10 0--.-- .................. \
+ 110000 ..... ..... ................ @PLS_D
+PLFD 000001 10 0--.-- .................. \
+ 110010 ..... ..... ................ @PLS_D
+PSTFS 000001 10 0--.-- .................. \
+ 110100 ..... ..... ................ @PLS_D
+PSTFD 000001 10 0--.-- .................. \
+ 110110 ..... ..... ................ @PLS_D
+
### Prefixed No-operation Instruction
@PNOP 000001 11 0000-- 000000000000000000 \
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 57a799db1c..d1dbb1b96b 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -1342,6 +1342,16 @@ static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store,
single);
}
+static bool do_lsfp_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
+ bool store, bool single)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return do_lsfp_D(ctx, &d, update, store, single);
+}
+
static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update,
bool store, bool single)
{
@@ -1352,21 +1362,25 @@ TRANS(LFS, do_lsfp_D, false, false, true)
TRANS(LFSU, do_lsfp_D, true, false, true)
TRANS(LFSX, do_lsfp_X, false, false, true)
TRANS(LFSUX, do_lsfp_X, true, false, true)
+TRANS(PLFS, do_lsfp_PLS_D, false, false, true)
TRANS(LFD, do_lsfp_D, false, false, false)
TRANS(LFDU, do_lsfp_D, true, false, false)
TRANS(LFDX, do_lsfp_X, false, false, false)
TRANS(LFDUX, do_lsfp_X, true, false, false)
+TRANS(PLFD, do_lsfp_PLS_D, false, false, false)
TRANS(STFS, do_lsfp_D, false, true, true)
TRANS(STFSU, do_lsfp_D, true, true, true)
TRANS(STFSX, do_lsfp_X, false, true, true)
TRANS(STFSUX, do_lsfp_X, true, true, true)
+TRANS(PSTFS, do_lsfp_PLS_D, false, true, true)
TRANS(STFD, do_lsfp_D, false, true, false)
TRANS(STFDU, do_lsfp_D, true, true, false)
TRANS(STFDX, do_lsfp_X, false, true, false)
TRANS(STFDUX, do_lsfp_X, true, true, false)
+TRANS(PSTFD, do_lsfp_PLS_D, false, true, false)
#undef _GEN_FLOAT_ACB
#undef GEN_FLOAT_ACB
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 05/54] target/ppc: Move LQ and STQ to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (3 preceding siblings ...)
2021-11-09 5:51 ` [PULL 04/54] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 06/54] target/ppc: Implement PLQ and PSTQ David Gibson
` (49 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-6-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 11 ++
target/ppc/translate.c | 156 +--------------------
target/ppc/translate/fixedpoint-impl.c.inc | 97 +++++++++++++
3 files changed, 113 insertions(+), 151 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 19ef9bff67..7ff8c25ac5 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -24,9 +24,16 @@
@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
+%dq_si 4:s12 !function=times_16
+%dq_rtp 22:4 !function=times_2
+@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+%ds_rtp 22:4 !function=times_2
+@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
+
&DX rt d
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
@@ -74,6 +81,8 @@ LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
+LQ 111000 ..... ..... ............ ---- @DQ_rtp
+
### Fixed-Point Store Instructions
STB 100110 ..... ..... ................ @D
@@ -96,6 +105,8 @@ STDU 111110 ..... ..... ..............01 @DS
STDX 011111 ..... ..... ..... 0010010101 - @X
STDUX 011111 ..... ..... ..... 0010110101 - @X
+STQ 111110 ..... ..... ..............10 @DS_rtp
+
### Fixed-Point Compare Instructions
CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3f50f44c19..8d5141497f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3327,69 +3327,6 @@ GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
-
-/* lq */
-static void gen_lq(DisasContext *ctx)
-{
- int ra, rd;
- TCGv EA, hi, lo;
-
- /* lq is a legal user mode instruction starting in ISA 2.07 */
- bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
- bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
-
- if (!legal_in_user_mode && ctx->pr) {
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
- return;
- }
-
- if (!le_is_supported && ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
- ra = rA(ctx->opcode);
- rd = rD(ctx->opcode);
- if (unlikely((rd & 1) || rd == ra)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
-
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x0F);
-
- /* Note that the low part is always in RD+1, even in LE mode. */
- lo = cpu_gpr[rd + 1];
- hi = cpu_gpr[rd];
-
- if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
- if (HAVE_ATOMIC128) {
- TCGv_i32 oi = tcg_temp_new_i32();
- if (ctx->le_mode) {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
- gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
- } else {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
- gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
- }
- tcg_temp_free_i32(oi);
- tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
- } else {
- /* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
- ctx->base.is_jmp = DISAS_NORETURN;
- }
- } else if (ctx->le_mode) {
- tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
- } else {
- tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
- }
- tcg_temp_free(EA);
-}
#endif
/*** Integer store ***/
@@ -3435,90 +3372,6 @@ GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
-
-static void gen_std(DisasContext *ctx)
-{
- int rs;
- TCGv EA;
-
- rs = rS(ctx->opcode);
- if ((ctx->opcode & 0x3) == 0x2) { /* stq */
- bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
- bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
- TCGv hi, lo;
-
- if (!(ctx->insns_flags & PPC_64BX)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- }
-
- if (!legal_in_user_mode && ctx->pr) {
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
- return;
- }
-
- if (!le_is_supported && ctx->le_mode) {
- gen_align_no_le(ctx);
- return;
- }
-
- if (unlikely(rs & 1)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
-
- /* Note that the low part is always in RS+1, even in LE mode. */
- lo = cpu_gpr[rs + 1];
- hi = cpu_gpr[rs];
-
- if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
- if (HAVE_ATOMIC128) {
- TCGv_i32 oi = tcg_temp_new_i32();
- if (ctx->le_mode) {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128,
- ctx->mem_idx));
- gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
- } else {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128,
- ctx->mem_idx));
- gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
- }
- tcg_temp_free_i32(oi);
- } else {
- /* Restart with exclusive lock. */
- gen_helper_exit_atomic(cpu_env);
- ctx->base.is_jmp = DISAS_NORETURN;
- }
- } else if (ctx->le_mode) {
- tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
- } else {
- tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
- gen_addr_add(ctx, EA, EA, 8);
- tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
- }
- tcg_temp_free(EA);
- } else {
- /* std / stdu */
- if (Rc(ctx->opcode)) {
- if (unlikely(rA(ctx->opcode) == 0)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
- gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
- if (Rc(ctx->opcode)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
- }
- tcg_temp_free(EA);
- }
-}
#endif
/*** Integer load and store with byte reverse ***/
@@ -7457,6 +7310,11 @@ static int times_4(DisasContext *ctx, int x)
return x * 4;
}
+static int times_16(DisasContext *ctx, int x)
+{
+ return x * 16;
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
@@ -7696,10 +7554,6 @@ GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
PPC_NONE, PPC2_ISA300),
#endif
-#if defined(TARGET_PPC64)
-GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
-GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
-#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
/* handles stfdp, lxv, stxsd, stxssp, stxv */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 812b7ddd0a..ff35a96459 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -69,6 +69,97 @@ static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
}
+static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
+{
+#if defined(TARGET_PPC64)
+ TCGv ea;
+ TCGv_i64 low_addr_gpr, high_addr_gpr;
+ MemOp mop;
+
+ REQUIRE_INSNS_FLAGS(ctx, 64BX);
+
+ if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
+ if (ctx->pr) {
+ /* lq and stq were privileged prior to V. 2.07 */
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+ return true;
+ }
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return true;
+ }
+ }
+
+ if (!store && unlikely(a->ra == a->rt)) {
+ gen_invalid(ctx);
+ return true;
+ }
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si));
+
+ if (prefixed || !ctx->le_mode) {
+ low_addr_gpr = cpu_gpr[a->rt];
+ high_addr_gpr = cpu_gpr[a->rt + 1];
+ } else {
+ low_addr_gpr = cpu_gpr[a->rt + 1];
+ high_addr_gpr = cpu_gpr[a->rt];
+ }
+
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ if (HAVE_ATOMIC128) {
+ mop = DEF_MEMOP(MO_128);
+ TCGv_i32 oi = tcg_constant_i32(make_memop_idx(mop, ctx->mem_idx));
+ if (store) {
+ if (ctx->le_mode) {
+ gen_helper_stq_le_parallel(cpu_env, ea, low_addr_gpr,
+ high_addr_gpr, oi);
+ } else {
+ gen_helper_stq_be_parallel(cpu_env, ea, high_addr_gpr,
+ low_addr_gpr, oi);
+
+ }
+ } else {
+ if (ctx->le_mode) {
+ gen_helper_lq_le_parallel(low_addr_gpr, cpu_env, ea, oi);
+ tcg_gen_ld_i64(high_addr_gpr, cpu_env,
+ offsetof(CPUPPCState, retxh));
+ } else {
+ gen_helper_lq_be_parallel(high_addr_gpr, cpu_env, ea, oi);
+ tcg_gen_ld_i64(low_addr_gpr, cpu_env,
+ offsetof(CPUPPCState, retxh));
+ }
+ }
+ } else {
+ /* Restart with exclusive lock. */
+ gen_helper_exit_atomic(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ }
+ } else {
+ mop = DEF_MEMOP(MO_Q);
+ if (store) {
+ tcg_gen_qemu_st_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(low_addr_gpr, ea, ctx->mem_idx, mop);
+ }
+
+ gen_addr_add(ctx, ea, ea, 8);
+
+ if (store) {
+ tcg_gen_qemu_st_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
+ }
+ }
+ tcg_temp_free(ea);
+#else
+ qemu_build_not_reached();
+#endif
+
+ return true;
+}
+
/* Load Byte and Zero */
TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
@@ -110,6 +201,9 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
+/* Load Quadword */
+TRANS64(LQ, do_ldst_quad, false, false);
+
/* Store Byte */
TRANS(STB, do_ldst_D, false, true, MO_UB)
TRANS(STBX, do_ldst_X, false, true, MO_UB)
@@ -138,6 +232,9 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
+/* Store Quadword */
+TRANS64(STQ, do_ldst_quad, true, false);
+
/*
* Fixed-Point Compare Instructions
*/
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 06/54] target/ppc: Implement PLQ and PSTQ
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (4 preceding siblings ...)
2021-11-09 5:51 ` [PULL 05/54] target/ppc: Move LQ and STQ to decodetree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 07/54] target/ppc: Implement cntlzdm David Gibson
` (48 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-7-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 4 ++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 11e5ea81d6..48756cd4ca 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -38,6 +38,8 @@ PLWA 000001 00 0--.-- .................. \
101001 ..... ..... ................ @PLS_D
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+PLQ 000001 00 0--.-- .................. \
+ 111000 ..... ..... ................ @PLS_D
### Fixed-Point Store Instructions
@@ -50,6 +52,8 @@ PSTH 000001 10 0--.-- .................. \
PSTD 000001 00 0--.-- .................. \
111101 ..... ..... ................ @PLS_D
+PSTQ 000001 00 0--.-- .................. \
+ 111100 ..... ..... ................ @PLS_D
### Fixed-Point Arithmetic Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index ff35a96459..0d9c6e0996 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -160,6 +160,16 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
return true;
}
+static bool do_ldst_quad_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_ldst_quad(ctx, &d, store, true);
+}
+
/* Load Byte and Zero */
TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
@@ -203,6 +213,7 @@ TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/* Load Quadword */
TRANS64(LQ, do_ldst_quad, false, false);
+TRANS64(PLQ, do_ldst_quad_PLS_D, false);
/* Store Byte */
TRANS(STB, do_ldst_D, false, true, MO_UB)
@@ -234,6 +245,7 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/* Store Quadword */
TRANS64(STQ, do_ldst_quad, true, false);
+TRANS64(PSTQ, do_ldst_quad_PLS_D, true);
/*
* Fixed-Point Compare Instructions
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 07/54] target/ppc: Implement cntlzdm
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (5 preceding siblings ...)
2021-11-09 5:51 ` [PULL 06/54] target/ppc: Implement PLQ and PSTQ David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 08/54] target/ppc: Implement cnttzdm David Gibson
` (47 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Matheus Ferst, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-8-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 36 ++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 7ff8c25ac5..eb3383c99c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -124,6 +124,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
+CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 0d9c6e0996..c9e9ae35df 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+#if defined(TARGET_PPC64)
+static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
+{
+ TCGv_i64 tmp;
+ TCGLabel *l1;
+
+ tmp = tcg_temp_local_new_i64();
+ l1 = gen_new_label();
+
+ tcg_gen_and_i64(tmp, src, mask);
+ tcg_gen_clzi_i64(tmp, tmp, 64);
+
+ tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
+
+ tcg_gen_subfi_i64(tmp, 64, tmp);
+ tcg_gen_shr_i64(tmp, mask, tmp);
+ tcg_gen_ctpop_i64(tmp, tmp);
+
+ gen_set_label(l1);
+
+ tcg_gen_mov_i64(dst, tmp);
+}
+#endif
+
+static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 08/54] target/ppc: Implement cnttzdm
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (6 preceding siblings ...)
2021-11-09 5:51 ` [PULL 07/54] target/ppc: Implement cntlzdm David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 09/54] target/ppc: Implement pdepd instruction David Gibson
` (46 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Matheus Ferst, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cnttzdm: Count Trailing Zeros Doubleword Under Bit Mask
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-9-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 28 ++++++++++++++++++----
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index eb3383c99c..ee8c90d520 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -125,6 +125,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
+CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index c9e9ae35df..d3dc0a474e 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -415,7 +415,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
}
#if defined(TARGET_PPC64)
-static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
+static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
{
TCGv_i64 tmp;
TCGLabel *l1;
@@ -424,12 +424,20 @@ static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
l1 = gen_new_label();
tcg_gen_and_i64(tmp, src, mask);
- tcg_gen_clzi_i64(tmp, tmp, 64);
+ if (trail) {
+ tcg_gen_ctzi_i64(tmp, tmp, 64);
+ } else {
+ tcg_gen_clzi_i64(tmp, tmp, 64);
+ }
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
tcg_gen_subfi_i64(tmp, 64, tmp);
- tcg_gen_shr_i64(tmp, mask, tmp);
+ if (trail) {
+ tcg_gen_shl_i64(tmp, mask, tmp);
+ } else {
+ tcg_gen_shr_i64(tmp, mask, tmp);
+ }
tcg_gen_ctpop_i64(tmp, tmp);
gen_set_label(l1);
@@ -443,7 +451,19 @@ static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
- do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], false);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ do_cntzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb], true);
#else
qemu_build_not_reached();
#endif
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 09/54] target/ppc: Implement pdepd instruction
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (7 preceding siblings ...)
2021-11-09 5:51 ` [PULL 08/54] target/ppc: Implement cnttzdm David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 10/54] target/ppc: Implement pextd instruction David Gibson
` (45 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-10-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 20 ++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 34 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4076aa281e..3e22957559 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -48,6 +48,7 @@ DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
+DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index ee8c90d520..c47a6a02e1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -126,6 +126,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
+PDEPD 011111 ..... ..... ..... 0010011100 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index eeb7781a9e..337bb7f4d3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -386,6 +386,26 @@ uint64_t helper_cfuged(uint64_t src, uint64_t mask)
return left | (right >> n);
}
+#if defined(TARGET_PPC64)
+uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
+{
+ int i, o;
+ uint64_t result = 0;
+
+ if (mask == -1) {
+ return src;
+ }
+
+ for (i = 0; mask != 0; i++) {
+ o = ctz64(mask);
+ mask &= mask - 1;
+ result |= ((src >> i) & 1) << o;
+ }
+
+ return result;
+}
+#endif
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index d3dc0a474e..f0bf69fbac 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -469,3 +469,15 @@ static bool trans_CNTTZDM(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_PDEPD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 10/54] target/ppc: Implement pextd instruction
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (8 preceding siblings ...)
2021-11-09 5:51 ` [PULL 09/54] target/ppc: Implement pdepd instruction David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128 David Gibson
` (44 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-11-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 18 ++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3e22957559..808c582382 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -49,6 +49,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c47a6a02e1..e13f920702 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -127,6 +127,7 @@ CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
PDEPD 011111 ..... ..... ..... 0010011100 - @X
+PEXTD 011111 ..... ..... ..... 0010111100 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 337bb7f4d3..913d76be6e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -404,6 +404,24 @@ uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
return result;
}
+
+uint64_t helper_PEXTD(uint64_t src, uint64_t mask)
+{
+ int i, o;
+ uint64_t result = 0;
+
+ if (mask == -1) {
+ return src;
+ }
+
+ for (o = 0; mask != 0; o++) {
+ i = ctz64(mask);
+ mask &= mask - 1;
+ result |= ((src >> i) & 1) << o;
+ }
+
+ return result;
+}
#endif
/*****************************************************************************/
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index f0bf69fbac..220b099fcd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -481,3 +481,15 @@ static bool trans_PDEPD(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_PEXTD(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (9 preceding siblings ...)
2021-11-09 5:51 ` [PULL 10/54] target/ppc: Implement pextd instruction David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c David Gibson
` (43 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
This will be used to implement PowerPC's dcffixqq.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-2-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/libdecnumber/decNumber.h | 2 ++
libdecnumber/decNumber.c | 36 ++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/include/libdecnumber/decNumber.h b/include/libdecnumber/decNumber.h
index aa115fed07..0cf69c7db2 100644
--- a/include/libdecnumber/decNumber.h
+++ b/include/libdecnumber/decNumber.h
@@ -116,6 +116,8 @@
decNumber * decNumberFromUInt32(decNumber *, uint32_t);
decNumber *decNumberFromInt64(decNumber *, int64_t);
decNumber *decNumberFromUInt64(decNumber *, uint64_t);
+ decNumber *decNumberFromInt128(decNumber *, uint64_t, int64_t);
+ decNumber *decNumberFromUInt128(decNumber *, uint64_t, uint64_t);
decNumber * decNumberFromString(decNumber *, const char *, decContext *);
char * decNumberToString(const decNumber *, char *);
char * decNumberToEngString(const decNumber *, char *);
diff --git a/libdecnumber/decNumber.c b/libdecnumber/decNumber.c
index 1ffe458ad8..d7716ce175 100644
--- a/libdecnumber/decNumber.c
+++ b/libdecnumber/decNumber.c
@@ -167,6 +167,7 @@
/* ------------------------------------------------------------------ */
#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
#include "libdecnumber/dconfig.h"
#include "libdecnumber/decNumber.h"
#include "libdecnumber/decNumberLocal.h"
@@ -462,6 +463,41 @@ decNumber *decNumberFromUInt64(decNumber *dn, uint64_t uin)
return dn;
} /* decNumberFromUInt64 */
+decNumber *decNumberFromInt128(decNumber *dn, uint64_t lo, int64_t hi)
+{
+ uint64_t unsig_hi = hi;
+ if (hi < 0) {
+ if (lo == 0) {
+ unsig_hi = -unsig_hi;
+ } else {
+ unsig_hi = ~unsig_hi;
+ lo = -lo;
+ }
+ }
+
+ decNumberFromUInt128(dn, lo, unsig_hi);
+ if (hi < 0) {
+ dn->bits = DECNEG; /* sign needed */
+ }
+ return dn;
+} /* decNumberFromInt128 */
+
+decNumber *decNumberFromUInt128(decNumber *dn, uint64_t lo, uint64_t hi)
+{
+ uint64_t rem;
+ Unit *up; /* work pointer */
+ decNumberZero(dn); /* clean */
+ if (lo == 0 && hi == 0) {
+ return dn; /* [or decGetDigits bad call] */
+ }
+ for (up = dn->lsu; hi > 0 || lo > 0; up++) {
+ rem = divu128(&lo, &hi, DECDPUNMAX + 1);
+ *up = (Unit)rem;
+ }
+ dn->digits = decGetDigits(dn->lsu, up - dn->lsu);
+ return dn;
+} /* decNumberFromUInt128 */
+
/* ------------------------------------------------------------------ */
/* to-int64 -- conversion to int64 */
/* */
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (10 preceding siblings ...)
2021-11-09 5:51 ` [PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128 David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 13/54] target/ppc: Introduce REQUIRE_FPU David Gibson
` (42 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, Fernando Valle, qemu-ppc, Bruno Larsen, Matheus Ferst,
David Gibson
From: Bruno Larsen <bruno.larsen@eldorado.org.br>
Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR.
Signed-off-by: Bruno Larsen <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Fernando Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211029192417.400707-3-luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 8 ++++++++
target/ppc/translate/vector-impl.c.inc | 10 +---------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8d5141497f..1d24b85746 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7341,6 +7341,14 @@ static int times_16(DisasContext *ctx, int x)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+#define REQUIRE_VECTOR(CTX) \
+ do { \
+ if (unlikely(!(CTX)->altivec_enabled)) { \
+ gen_exception((CTX), POWERPC_EXCP_VPU); \
+ return true; \
+ } \
+ } while (0)
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
index 117ce9b137..197e903337 100644
--- a/target/ppc/translate/vector-impl.c.inc
+++ b/target/ppc/translate/vector-impl.c.inc
@@ -17,20 +17,12 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-#define REQUIRE_ALTIVEC(CTX) \
- do { \
- if (unlikely(!(CTX)->altivec_enabled)) { \
- gen_exception((CTX), POWERPC_EXCP_VPU); \
- return true; \
- } \
- } while (0)
-
static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
{
TCGv_i64 tgt, src, mask;
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
- REQUIRE_ALTIVEC(ctx);
+ REQUIRE_VECTOR(ctx);
tgt = tcg_temp_new_i64();
src = tcg_temp_new_i64();
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 13/54] target/ppc: Introduce REQUIRE_FPU
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (11 preceding siblings ...)
2021-11-09 5:51 ` [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 14/54] target/ppc: Implement DCFFIXQQ David Gibson
` (41 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, Fernando Valle, qemu-ppc, David Gibson
From: Fernando Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Fernando Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-4-luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1d24b85746..d4e72affa6 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7349,6 +7349,14 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#define REQUIRE_FPU(ctx) \
+ do { \
+ if (unlikely(!(ctx)->fpu_enabled)) { \
+ gen_exception((ctx), POWERPC_EXCP_FPU); \
+ return true; \
+ } \
+ } while (0)
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 14/54] target/ppc: Implement DCFFIXQQ
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (12 preceding siblings ...)
2021-11-09 5:51 ` [PULL 13/54] target/ppc: Introduce REQUIRE_FPU David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 15/54] host-utils: Introduce mulu128 David Gibson
` (40 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
dcffixqq: DFP Convert From Fixed Quadword Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-5-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 12 ++++++++++++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 8 ++++++++
target/ppc/translate.c | 5 +++++
target/ppc/translate/dfp-impl.c.inc | 17 +++++++++++++++++
5 files changed, 43 insertions(+)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 07341a69f5..6b837c4450 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -970,6 +970,18 @@ static void CFFIX_PPs(struct PPC_DFP *dfp)
DFP_HELPER_CFFIX(dcffix, 64)
DFP_HELPER_CFFIX(dcffixq, 128)
+void helper_DCFFIXQQ(CPUPPCState *env, ppc_fprp_t *t, ppc_avr_t *b)
+{
+ struct PPC_DFP dfp;
+
+ dfp_prepare_decimal128(&dfp, NULL, NULL, env);
+ decNumberFromInt128(&dfp.t, (uint64_t)b->VsrD(1), (int64_t)b->VsrD(0));
+ dfp_finalize_decimal128(&dfp);
+ CFFIX_PPs(&dfp);
+
+ set_dfp128(t, &dfp.vt);
+}
+
#define DFP_HELPER_CTFIX(op, size) \
void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
{ \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 808c582382..8e4f67ceac 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -736,6 +736,7 @@ DEF_HELPER_3(drsp, void, env, fprp, fprp)
DEF_HELPER_3(drdpq, void, env, fprp, fprp)
DEF_HELPER_3(dcffix, void, env, fprp, fprp)
DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
+DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
DEF_HELPER_3(dctfix, void, env, fprp, fprp)
DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e13f920702..36586dfa59 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -50,6 +50,10 @@
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+&X_frtp_vrb frtp vrb
+%x_frtp 22:4 !function=times_2
+@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -160,6 +164,10 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+### Decimal Floating-Point Conversion Instructions
+
+DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d4e72affa6..486339d402 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7305,6 +7305,11 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
/*
* Helpers for decodetree used by !function for decoding arguments.
*/
+static int times_2(DisasContext *ctx, int x)
+{
+ return x * 2;
+}
+
static int times_4(DisasContext *ctx, int x)
{
return x * 4;
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 6c556dc2e1..d5b66567a6 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -230,3 +230,20 @@ GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
#undef GEN_DFP_T_A_B_I32_Rc
#undef GEN_DFP_T_B_Rc
#undef GEN_DFP_T_FPR_I32_Rc
+
+static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
+{
+ TCGv_ptr rt, rb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, DFP);
+ REQUIRE_FPU(ctx);
+ REQUIRE_VECTOR(ctx);
+
+ rt = gen_fprp_ptr(a->frtp);
+ rb = gen_avr_ptr(a->vrb);
+ gen_helper_DCFFIXQQ(cpu_env, rt, rb);
+ tcg_temp_free_ptr(rt);
+ tcg_temp_free_ptr(rb);
+
+ return true;
+}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 15/54] host-utils: Introduce mulu128
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (13 preceding siblings ...)
2021-11-09 5:51 ` [PULL 14/54] target/ppc: Implement DCFFIXQQ David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128 David Gibson
` (39 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-6-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/qemu/host-utils.h | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index a3a7ced78d..ca979dc6cc 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -590,6 +590,42 @@ static inline bool umul64_overflow(uint64_t x, uint64_t y, uint64_t *ret)
#endif
}
+/*
+ * Unsigned 128x64 multiplication.
+ * Returns true if the result got truncated to 128 bits.
+ * Otherwise, returns false and the multiplication result via plow and phigh.
+ */
+static inline bool mulu128(uint64_t *plow, uint64_t *phigh, uint64_t factor)
+{
+#if defined(CONFIG_INT128) && \
+ (__has_builtin(__builtin_mul_overflow) || __GNUC__ >= 5)
+ bool res;
+ __uint128_t r;
+ __uint128_t f = ((__uint128_t)*phigh << 64) | *plow;
+ res = __builtin_mul_overflow(f, factor, &r);
+
+ *plow = r;
+ *phigh = r >> 64;
+
+ return res;
+#else
+ uint64_t dhi = *phigh;
+ uint64_t dlo = *plow;
+ uint64_t ahi;
+ uint64_t blo, bhi;
+
+ if (dhi == 0) {
+ mulu64(plow, phigh, dlo, factor);
+ return false;
+ }
+
+ mulu64(plow, &ahi, dlo, factor);
+ mulu64(&blo, &bhi, dhi, factor);
+
+ return uadd64_overflow(ahi, blo, phigh) || bhi != 0;
+#endif
+}
+
/**
* uadd64_carry - addition with carry-in and carry-out
* @x, @y: addends
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (14 preceding siblings ...)
2021-11-09 5:51 ` [PULL 15/54] host-utils: Introduce mulu128 David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 17/54] target/ppc: Implement DCTFIXQQ David Gibson
` (38 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
This will be used to implement PowerPC's dctfixqq.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-7-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/libdecnumber/decNumber.h | 2 +
include/libdecnumber/decNumberLocal.h | 2 +-
libdecnumber/decContext.c | 7 +-
libdecnumber/decNumber.c | 95 +++++++++++++++++++++++++++
4 files changed, 102 insertions(+), 4 deletions(-)
diff --git a/include/libdecnumber/decNumber.h b/include/libdecnumber/decNumber.h
index 0cf69c7db2..41bc2a0d36 100644
--- a/include/libdecnumber/decNumber.h
+++ b/include/libdecnumber/decNumber.h
@@ -124,6 +124,8 @@
uint32_t decNumberToUInt32(const decNumber *, decContext *);
int32_t decNumberToInt32(const decNumber *, decContext *);
int64_t decNumberIntegralToInt64(const decNumber *dn, decContext *set);
+ void decNumberIntegralToInt128(const decNumber *dn, decContext *set,
+ uint64_t *plow, uint64_t *phigh);
uint8_t * decNumberGetBCD(const decNumber *, uint8_t *);
decNumber * decNumberSetBCD(decNumber *, const uint8_t *, uint32_t);
diff --git a/include/libdecnumber/decNumberLocal.h b/include/libdecnumber/decNumberLocal.h
index 4d53c077f2..6198ca8593 100644
--- a/include/libdecnumber/decNumberLocal.h
+++ b/include/libdecnumber/decNumberLocal.h
@@ -98,7 +98,7 @@
/* Shared lookup tables */
extern const uByte DECSTICKYTAB[10]; /* re-round digits if sticky */
- extern const uLong DECPOWERS[19]; /* powers of ten table */
+ extern const uLong DECPOWERS[20]; /* powers of ten table */
/* The following are included from decDPD.h */
extern const uShort DPD2BIN[1024]; /* DPD -> 0-999 */
extern const uShort BIN2DPD[1000]; /* 0-999 -> DPD */
diff --git a/libdecnumber/decContext.c b/libdecnumber/decContext.c
index 7d97a65ac5..1956edf0a7 100644
--- a/libdecnumber/decContext.c
+++ b/libdecnumber/decContext.c
@@ -53,12 +53,13 @@ static const Flag *mfctop=(Flag *)&mfcone; /* -> top byte */
const uByte DECSTICKYTAB[10]={1,1,2,3,4,6,6,7,8,9}; /* used if sticky */
/* ------------------------------------------------------------------ */
-/* Powers of ten (powers[n]==10**n, 0<=n<=9) */
+/* Powers of ten (powers[n]==10**n, 0<=n<=19) */
/* ------------------------------------------------------------------ */
-const uLong DECPOWERS[19] = {1, 10, 100, 1000, 10000, 100000, 1000000,
+const uLong DECPOWERS[20] = {1, 10, 100, 1000, 10000, 100000, 1000000,
10000000, 100000000, 1000000000, 10000000000ULL, 100000000000ULL,
1000000000000ULL, 10000000000000ULL, 100000000000000ULL, 1000000000000000ULL,
- 10000000000000000ULL, 100000000000000000ULL, 1000000000000000000ULL, };
+ 10000000000000000ULL, 100000000000000000ULL, 1000000000000000000ULL,
+ 10000000000000000000ULL,};
/* ------------------------------------------------------------------ */
/* decContextClearStatus -- clear bits in current status */
diff --git a/libdecnumber/decNumber.c b/libdecnumber/decNumber.c
index d7716ce175..31282adafd 100644
--- a/libdecnumber/decNumber.c
+++ b/libdecnumber/decNumber.c
@@ -264,6 +264,7 @@ static decNumber * decTrim(decNumber *, decContext *, Flag, Int *);
static Int decUnitAddSub(const Unit *, Int, const Unit *, Int, Int,
Unit *, Int);
static Int decUnitCompare(const Unit *, Int, const Unit *, Int, Int);
+static bool mulUInt128ByPowOf10(uLong *, uLong *, uInt);
#if !DECSUBSET
/* decFinish == decFinalize when no subset arithmetic needed */
@@ -542,6 +543,68 @@ Invalid:
return 0;
} /* decNumberIntegralToInt64 */
+/* ------------------------------------------------------------------ */
+/* decNumberIntegralToInt128 -- conversion to int128 */
+/* */
+/* dn is the decNumber to convert. dn is assumed to have been */
+/* rounded to a floating point integer value. */
+/* set is the context for reporting errors */
+/* returns the converted decNumber via plow and phigh */
+/* */
+/* Invalid is set if the decNumber is a NaN, Infinite or is out of */
+/* range for a signed 128 bit integer. */
+/* ------------------------------------------------------------------ */
+
+void decNumberIntegralToInt128(const decNumber *dn, decContext *set,
+ uint64_t *plow, uint64_t *phigh)
+{
+ int d; /* work */
+ const Unit *up; /* .. */
+ uint64_t lo = 0, hi = 0;
+
+ if (decNumberIsSpecial(dn) || (dn->exponent < 0) ||
+ (dn->digits + dn->exponent > 39)) {
+ goto Invalid;
+ }
+
+ up = dn->lsu; /* -> lsu */
+
+ for (d = (dn->digits - 1) / DECDPUN; d >= 0; d--) {
+ if (mulu128(&lo, &hi, DECDPUNMAX + 1)) {
+ /* overflow */
+ goto Invalid;
+ }
+ if (uadd64_overflow(lo, up[d], &lo)) {
+ if (uadd64_overflow(hi, 1, &hi)) {
+ /* overflow */
+ goto Invalid;
+ }
+ }
+ }
+
+ if (mulUInt128ByPowOf10(&lo, &hi, dn->exponent)) {
+ /* overflow */
+ goto Invalid;
+ }
+
+ if (decNumberIsNegative(dn)) {
+ if (lo == 0) {
+ *phigh = -hi;
+ *plow = 0;
+ } else {
+ *phigh = ~hi;
+ *plow = -lo;
+ }
+ } else {
+ *plow = lo;
+ *phigh = hi;
+ }
+
+ return;
+
+Invalid:
+ decContextSetStatus(set, DEC_Invalid_operation);
+} /* decNumberIntegralToInt128 */
/* ------------------------------------------------------------------ */
/* to-scientific-string -- conversion to numeric string */
@@ -7885,6 +7948,38 @@ static Int decGetDigits(Unit *uar, Int len) {
return digits;
} /* decGetDigits */
+/* ------------------------------------------------------------------ */
+/* mulUInt128ByPowOf10 -- multiply a 128-bit unsigned integer by a */
+/* power of 10. */
+/* */
+/* The 128-bit factor composed of plow and phigh is multiplied */
+/* by 10^exp. */
+/* */
+/* plow pointer to the low 64 bits of the first factor */
+/* phigh pointer to the high 64 bits of the first factor */
+/* exp the exponent of the power of 10 of the second factor */
+/* */
+/* If the result fits in 128 bits, returns false and the */
+/* multiplication result through plow and phigh. */
+/* Otherwise, returns true. */
+/* ------------------------------------------------------------------ */
+static bool mulUInt128ByPowOf10(uLong *plow, uLong *phigh, uInt pow10)
+{
+ while (pow10 >= ARRAY_SIZE(powers)) {
+ if (mulu128(plow, phigh, powers[ARRAY_SIZE(powers) - 1])) {
+ /* Overflow */
+ return true;
+ }
+ pow10 -= ARRAY_SIZE(powers) - 1;
+ }
+
+ if (pow10 > 0) {
+ return mulu128(plow, phigh, powers[pow10]);
+ } else {
+ return false;
+ }
+}
+
#if DECTRACE | DECCHECK
/* ------------------------------------------------------------------ */
/* decNumberShow -- display a number [debug aid] */
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 17/54] target/ppc: Implement DCTFIXQQ
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (15 preceding siblings ...)
2021-11-09 5:51 ` [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128 David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 18/54] target/ppc: Do not update nip on DFP instructions David Gibson
` (37 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
dctfixqq: DFP Convert To Fixed Quadword Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-8-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 52 +++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 5 +++
target/ppc/translate/dfp-impl.c.inc | 17 ++++++++++
4 files changed, 75 insertions(+)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 6b837c4450..6ab46d7db5 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -51,6 +51,11 @@ static void set_dfp128(ppc_fprp_t *dfp, ppc_vsr_t *src)
dfp[1].VsrD(0) = src->VsrD(1);
}
+static void set_dfp128_to_avr(ppc_avr_t *dst, ppc_vsr_t *src)
+{
+ *dst = *src;
+}
+
struct PPC_DFP {
CPUPPCState *env;
ppc_vsr_t vt, va, vb;
@@ -1020,6 +1025,53 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
DFP_HELPER_CTFIX(dctfix, 64)
DFP_HELPER_CTFIX(dctfixq, 128)
+void helper_DCTFIXQQ(CPUPPCState *env, ppc_avr_t *t, ppc_fprp_t *b)
+{
+ struct PPC_DFP dfp;
+ dfp_prepare_decimal128(&dfp, 0, b, env);
+
+ if (unlikely(decNumberIsSpecial(&dfp.b))) {
+ uint64_t invalid_flags = FP_VX | FP_VXCVI;
+ if (decNumberIsInfinite(&dfp.b)) {
+ if (decNumberIsNegative(&dfp.b)) {
+ dfp.vt.VsrD(0) = INT64_MIN;
+ dfp.vt.VsrD(1) = 0;
+ } else {
+ dfp.vt.VsrD(0) = INT64_MAX;
+ dfp.vt.VsrD(1) = UINT64_MAX;
+ }
+ } else { /* NaN */
+ dfp.vt.VsrD(0) = INT64_MIN;
+ dfp.vt.VsrD(1) = 0;
+ if (decNumberIsSNaN(&dfp.b)) {
+ invalid_flags |= FP_VXSNAN;
+ }
+ }
+ dfp_set_FPSCR_flag(&dfp, invalid_flags, FP_VE);
+ } else if (unlikely(decNumberIsZero(&dfp.b))) {
+ dfp.vt.VsrD(0) = 0;
+ dfp.vt.VsrD(1) = 0;
+ } else {
+ decNumberToIntegralExact(&dfp.b, &dfp.b, &dfp.context);
+ decNumberIntegralToInt128(&dfp.b, &dfp.context,
+ &dfp.vt.VsrD(1), &dfp.vt.VsrD(0));
+ if (decContextTestStatus(&dfp.context, DEC_Invalid_operation)) {
+ if (decNumberIsNegative(&dfp.b)) {
+ dfp.vt.VsrD(0) = INT64_MIN;
+ dfp.vt.VsrD(1) = 0;
+ } else {
+ dfp.vt.VsrD(0) = INT64_MAX;
+ dfp.vt.VsrD(1) = UINT64_MAX;
+ }
+ dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FP_VE);
+ } else {
+ dfp_check_for_XX(&dfp);
+ }
+ }
+
+ set_dfp128_to_avr(t, &dfp.vt);
+}
+
static inline void dfp_set_bcd_digit_64(ppc_vsr_t *t, uint8_t digit,
unsigned n)
{
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8e4f67ceac..3812bb0270 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -739,6 +739,7 @@ DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
DEF_HELPER_3(dctfix, void, env, fprp, fprp)
DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
+DEF_HELPER_3(DCTFIXQQ, void, env, avr, fprp)
DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
DEF_HELPER_4(ddedpdq, void, env, fprp, fprp, i32)
DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 36586dfa59..33463c14ea 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -54,6 +54,10 @@
%x_frtp 22:4 !function=times_2
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
+&X_vrt_frbp vrt frbp
+%x_frbp 12:4 !function=times_2
+@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -167,6 +171,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
### Decimal Floating-Point Conversion Instructions
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
+DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp
## Vector Bit Manipulation Instruction
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index d5b66567a6..e149777481 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -247,3 +247,20 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
return true;
}
+
+static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFIXQQ *a)
+{
+ TCGv_ptr rt, rb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, DFP);
+ REQUIRE_FPU(ctx);
+ REQUIRE_VECTOR(ctx);
+
+ rt = gen_avr_ptr(a->vrt);
+ rb = gen_fprp_ptr(a->frbp);
+ gen_helper_DCTFIXQQ(cpu_env, rt, rb);
+ tcg_temp_free_ptr(rt);
+ tcg_temp_free_ptr(rb);
+
+ return true;
+}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 18/54] target/ppc: Do not update nip on DFP instructions
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (16 preceding siblings ...)
2021-11-09 5:51 ` [PULL 17/54] target/ppc: Implement DCTFIXQQ David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree David Gibson
` (36 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Before moving the existing DFP instructions to decodetree, drop the
nip update that shouldn't be done for these instructions.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-9-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/dfp-impl.c.inc | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index e149777481..1431d955c6 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -15,7 +15,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rd = gen_fprp_ptr(rD(ctx->opcode)); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
@@ -36,7 +35,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -54,7 +52,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
uim = tcg_const_i32(UIMM5(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -72,7 +69,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
dcm = tcg_const_i32(DCM(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -90,7 +86,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
@@ -114,7 +109,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
@@ -137,7 +131,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_env, rt, rb); \
@@ -157,7 +150,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
i32 = tcg_const_i32(i32fld(ctx->opcode)); \
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (17 preceding siblings ...)
2021-11-09 5:51 ` [PULL 18/54] target/ppc: Do not update nip on DFP instructions David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] " David Gibson
` (35 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, qemu-ppc, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
dtstdc: DFP Test Data Class
dtstdcq: DFP Test Data Class Quad
dtstdg: DFP Test Data Group
dtstdgq: DFP Test Data Group Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-10-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 8 +++----
target/ppc/helper.h | 8 +++----
target/ppc/insn32.decode | 14 ++++++++++++
target/ppc/translate/dfp-impl.c.inc | 35 +++++++++++++----------------
target/ppc/translate/dfp-ops.c.inc | 10 ---------
5 files changed, 37 insertions(+), 38 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 6ab46d7db5..f3c1e525a3 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -546,8 +546,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm) \
return dfp.crbf; \
}
-DFP_HELPER_TSTDC(dtstdc, 64)
-DFP_HELPER_TSTDC(dtstdcq, 128)
+DFP_HELPER_TSTDC(DTSTDC, 64)
+DFP_HELPER_TSTDC(DTSTDCQ, 128)
#define DFP_HELPER_TSTDG(op, size) \
uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm) \
@@ -601,8 +601,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm) \
return dfp.crbf; \
}
-DFP_HELPER_TSTDG(dtstdg, 64)
-DFP_HELPER_TSTDG(dtstdgq, 128)
+DFP_HELPER_TSTDG(DTSTDG, 64)
+DFP_HELPER_TSTDG(DTSTDGQ, 128)
#define DFP_HELPER_TSTEX(op, size) \
uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, ppc_fprp_t *b) \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3812bb0270..2f11411e14 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -710,10 +710,10 @@ DEF_HELPER_3(dcmpo, i32, env, fprp, fprp)
DEF_HELPER_3(dcmpoq, i32, env, fprp, fprp)
DEF_HELPER_3(dcmpu, i32, env, fprp, fprp)
DEF_HELPER_3(dcmpuq, i32, env, fprp, fprp)
-DEF_HELPER_3(dtstdc, i32, env, fprp, i32)
-DEF_HELPER_3(dtstdcq, i32, env, fprp, i32)
-DEF_HELPER_3(dtstdg, i32, env, fprp, i32)
-DEF_HELPER_3(dtstdgq, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDC, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDCQ, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDG, i32, env, fprp, i32)
+DEF_HELPER_3(DTSTDGQ, i32, env, fprp, i32)
DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 33463c14ea..49bdd3531e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -58,6 +58,12 @@
%x_frbp 12:4 !function=times_2
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+&Z22_bf_fra bf fra dm
+@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
+
+%z22_frap 17:4 !function=times_2
+@Z22_bf_frap ...... bf:3 .. ....0 dm:6 ......... . &Z22_bf_fra fra=%z22_frap
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -168,6 +174,14 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+### Decimal Floating-Point Test Instructions
+
+DTSTDC 111011 ... -- ..... ...... 011000010 - @Z22_bf_fra
+DTSTDCQ 111111 ... -- ..... ...... 011000010 - @Z22_bf_frap
+
+DTSTDG 111011 ... -- ..... ...... 011100010 - @Z22_bf_fra
+DTSTDGQ 111111 ... -- ..... ...... 011100010 - @Z22_bf_frap
+
### Decimal Floating-Point Conversion Instructions
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 1431d955c6..1a30c51467 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -60,21 +60,17 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_ptr(rb); \
}
-#define GEN_DFP_BF_A_DCM(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr ra; \
- TCGv_i32 dcm; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- dcm = tcg_const_i32(DCM(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
- cpu_env, ra, dcm); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_i32(dcm); \
+#define TRANS_DFP_BF_A_DCM(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr ra; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ ra = gen_fprp_ptr(a->fra); \
+ gen_helper_##NAME(cpu_crf[a->bf], \
+ cpu_env, ra, tcg_constant_i32(a->dm)); \
+ tcg_temp_free_ptr(ra); \
+ return true; \
}
#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
@@ -174,10 +170,10 @@ GEN_DFP_BF_A_B(dcmpu)
GEN_DFP_BF_A_B(dcmpuq)
GEN_DFP_BF_A_B(dcmpo)
GEN_DFP_BF_A_B(dcmpoq)
-GEN_DFP_BF_A_DCM(dtstdc)
-GEN_DFP_BF_A_DCM(dtstdcq)
-GEN_DFP_BF_A_DCM(dtstdg)
-GEN_DFP_BF_A_DCM(dtstdgq)
+TRANS_DFP_BF_A_DCM(DTSTDC)
+TRANS_DFP_BF_A_DCM(DTSTDCQ)
+TRANS_DFP_BF_A_DCM(DTSTDG)
+TRANS_DFP_BF_A_DCM(DTSTDGQ)
GEN_DFP_BF_A_B(dtstex)
GEN_DFP_BF_A_B(dtstexq)
GEN_DFP_BF_A_B(dtstsf)
@@ -217,7 +213,6 @@ GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
#undef GEN_DFP_T_A_B_Rc
#undef GEN_DFP_BF_A_B
-#undef GEN_DFP_BF_A_DCM
#undef GEN_DFP_T_B_U32_U32_Rc
#undef GEN_DFP_T_A_B_I32_Rc
#undef GEN_DFP_T_B_Rc
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index 6ef38e5712..e1df98d52e 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -66,12 +66,6 @@ _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \
_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001)
-#define GEN_DFP_BF_A_DCM(name, op1, op2) \
-_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
-
-#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
-_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
-
#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
@@ -123,10 +117,6 @@ GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
-GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
-GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
-GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
-GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (18 preceding siblings ...)
2021-11-09 5:51 ` [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] " David Gibson
` (34 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, qemu-ppc, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
dadd: DFP Add
daddq: DFP Add Quad
dsub: DFP Subtract
dsubq: DFP Subtract Quad
dmul: DFP Multiply
dmulq: DFP Multiply Quad
ddiv: DFP Divide
ddivq: DFP Divide Quad
diex: DFP Insert Biased Exponent
diexq: DFP Insert Biased Exponent Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-11-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 20 +++++------
target/ppc/helper.h | 20 +++++------
target/ppc/insn32.decode | 31 ++++++++++++++--
target/ppc/translate/dfp-impl.c.inc | 56 ++++++++++++++---------------
target/ppc/translate/dfp-ops.c.inc | 19 ----------
5 files changed, 76 insertions(+), 70 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index f3c1e525a3..da8eaaaff1 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -445,8 +445,8 @@ static void ADD_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXISI_add(dfp);
}
-DFP_HELPER_TAB(dadd, decNumberAdd, ADD_PPs, 64)
-DFP_HELPER_TAB(daddq, decNumberAdd, ADD_PPs, 128)
+DFP_HELPER_TAB(DADD, decNumberAdd, ADD_PPs, 64)
+DFP_HELPER_TAB(DADDQ, decNumberAdd, ADD_PPs, 128)
static void SUB_PPs(struct PPC_DFP *dfp)
{
@@ -458,8 +458,8 @@ static void SUB_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXISI_subtract(dfp);
}
-DFP_HELPER_TAB(dsub, decNumberSubtract, SUB_PPs, 64)
-DFP_HELPER_TAB(dsubq, decNumberSubtract, SUB_PPs, 128)
+DFP_HELPER_TAB(DSUB, decNumberSubtract, SUB_PPs, 64)
+DFP_HELPER_TAB(DSUBQ, decNumberSubtract, SUB_PPs, 128)
static void MUL_PPs(struct PPC_DFP *dfp)
{
@@ -471,8 +471,8 @@ static void MUL_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXIMZ(dfp);
}
-DFP_HELPER_TAB(dmul, decNumberMultiply, MUL_PPs, 64)
-DFP_HELPER_TAB(dmulq, decNumberMultiply, MUL_PPs, 128)
+DFP_HELPER_TAB(DMUL, decNumberMultiply, MUL_PPs, 64)
+DFP_HELPER_TAB(DMULQ, decNumberMultiply, MUL_PPs, 128)
static void DIV_PPs(struct PPC_DFP *dfp)
{
@@ -486,8 +486,8 @@ static void DIV_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXIDI(dfp);
}
-DFP_HELPER_TAB(ddiv, decNumberDivide, DIV_PPs, 64)
-DFP_HELPER_TAB(ddivq, decNumberDivide, DIV_PPs, 128)
+DFP_HELPER_TAB(DDIV, decNumberDivide, DIV_PPs, 64)
+DFP_HELPER_TAB(DDIVQ, decNumberDivide, DIV_PPs, 128)
#define DFP_HELPER_BF_AB(op, dnop, postprocs, size) \
uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, ppc_fprp_t *b) \
@@ -1299,8 +1299,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_IEX(diex, 64)
-DFP_HELPER_IEX(diexq, 128)
+DFP_HELPER_IEX(DIEX, 64)
+DFP_HELPER_IEX(DIEXQ, 128)
static void dfp_clear_lmd_from_g5msb(uint64_t *t)
{
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2f11411e14..f802392614 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -698,14 +698,14 @@ DEF_HELPER_3(store_601_batu, void, env, i32, tl)
#define dh_alias_fprp ptr
#define dh_ctype_fprp ppc_fprp_t *
-DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(dsub, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(dsubq, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(dmul, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(dmulq, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(ddiv, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(ddivq, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DADD, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DADDQ, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DSUB, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DSUBQ, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DMUL, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DMULQ, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DDIV, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DDIVQ, void, env, fprp, fprp, fprp)
DEF_HELPER_3(dcmpo, i32, env, fprp, fprp)
DEF_HELPER_3(dcmpoq, i32, env, fprp, fprp)
DEF_HELPER_3(dcmpu, i32, env, fprp, fprp)
@@ -746,8 +746,8 @@ DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32)
DEF_HELPER_4(denbcdq, void, env, fprp, fprp, i32)
DEF_HELPER_3(dxex, void, env, fprp, fprp)
DEF_HELPER_3(dxexq, void, env, fprp, fprp)
-DEF_HELPER_4(diex, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(diexq, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DIEX, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(DIEXQ, void, env, fprp, fprp, fprp)
DEF_HELPER_4(dscri, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscriq, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscli, void, env, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 49bdd3531e..bb3322dc00 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -44,6 +44,16 @@
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
+&X_rc rt ra rb rc:bool
+@X_rc ...... rt:5 ra:5 rb:5 .......... rc:1 &X_rc
+
+%x_frtp 22:4 !function=times_2
+%x_frap 17:4 !function=times_2
+%x_frbp 12:4 !function=times_2
+@X_tp_ap_bp_rc ...... ....0 ....0 ....0 .......... rc:1 &X_rc rt=%x_frtp ra=%x_frap rb=%x_frbp
+
+@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
+
&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
@@ -51,11 +61,9 @@
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
&X_frtp_vrb frtp vrb
-%x_frtp 22:4 !function=times_2
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
&X_vrt_frbp vrt frbp
-%x_frbp 12:4 !function=times_2
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
&Z22_bf_fra bf fra dm
@@ -174,6 +182,20 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+### Decimal Floating-Point Arithmetic Instructions
+
+DADD 111011 ..... ..... ..... 0000000010 . @X_rc
+DADDQ 111111 ..... ..... ..... 0000000010 . @X_tp_ap_bp_rc
+
+DSUB 111011 ..... ..... ..... 1000000010 . @X_rc
+DSUBQ 111111 ..... ..... ..... 1000000010 . @X_tp_ap_bp_rc
+
+DMUL 111011 ..... ..... ..... 0000100010 . @X_rc
+DMULQ 111111 ..... ..... ..... 0000100010 . @X_tp_ap_bp_rc
+
+DDIV 111011 ..... ..... ..... 1000100010 . @X_rc
+DDIVQ 111111 ..... ..... ..... 1000100010 . @X_tp_ap_bp_rc
+
### Decimal Floating-Point Test Instructions
DTSTDC 111011 ... -- ..... ...... 011000010 - @Z22_bf_fra
@@ -187,6 +209,11 @@ DTSTDGQ 111111 ... -- ..... ...... 011100010 - @Z22_bf_frap
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp
+### Decimal Floating-Point Format Instructions
+
+DIEX 111011 ..... ..... ..... 1101100010 . @X_rc
+DIEXQ 111111 ..... ..... ..... 1101100010 . @X_tp_a_bp_rc
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 1a30c51467..b08b38355b 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -7,24 +7,23 @@ static inline TCGv_ptr gen_fprp_ptr(int reg)
return r;
}
-#define GEN_DFP_T_A_B_Rc(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rd, ra, rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- rd = gen_fprp_ptr(rD(ctx->opcode)); \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_env, rd, ra, rb); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rd); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
+#define TRANS_DFP_T_A_B_Rc(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr rt, ra, rb; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ rt = gen_fprp_ptr(a->rt); \
+ ra = gen_fprp_ptr(a->ra); \
+ rb = gen_fprp_ptr(a->rb); \
+ gen_helper_##NAME(cpu_env, rt, ra, rb); \
+ if (unlikely(a->rc)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ return true; \
}
#define GEN_DFP_BF_A_B(name) \
@@ -158,14 +157,14 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i32(i32); \
}
-GEN_DFP_T_A_B_Rc(dadd)
-GEN_DFP_T_A_B_Rc(daddq)
-GEN_DFP_T_A_B_Rc(dsub)
-GEN_DFP_T_A_B_Rc(dsubq)
-GEN_DFP_T_A_B_Rc(dmul)
-GEN_DFP_T_A_B_Rc(dmulq)
-GEN_DFP_T_A_B_Rc(ddiv)
-GEN_DFP_T_A_B_Rc(ddivq)
+TRANS_DFP_T_A_B_Rc(DADD)
+TRANS_DFP_T_A_B_Rc(DADDQ)
+TRANS_DFP_T_A_B_Rc(DSUB)
+TRANS_DFP_T_A_B_Rc(DSUBQ)
+TRANS_DFP_T_A_B_Rc(DMUL)
+TRANS_DFP_T_A_B_Rc(DMULQ)
+TRANS_DFP_T_A_B_Rc(DDIV)
+TRANS_DFP_T_A_B_Rc(DDIVQ)
GEN_DFP_BF_A_B(dcmpu)
GEN_DFP_BF_A_B(dcmpuq)
GEN_DFP_BF_A_B(dcmpo)
@@ -204,14 +203,13 @@ GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
GEN_DFP_T_B_Rc(dxex)
GEN_DFP_T_B_Rc(dxexq)
-GEN_DFP_T_A_B_Rc(diex)
-GEN_DFP_T_A_B_Rc(diexq)
+TRANS_DFP_T_A_B_Rc(DIEX)
+TRANS_DFP_T_A_B_Rc(DIEXQ)
GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-#undef GEN_DFP_T_A_B_Rc
#undef GEN_DFP_BF_A_B
#undef GEN_DFP_T_B_U32_U32_Rc
#undef GEN_DFP_T_A_B_I32_Rc
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index e1df98d52e..38ea551488 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -30,15 +30,6 @@ GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
-
-#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
-
#define GEN_DFP_T_B_Rc(name, op1, op2) \
_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
@@ -105,14 +96,6 @@ _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
-GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
-GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
-GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
-GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
-GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
-GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
-GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
@@ -147,8 +130,6 @@ GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
-GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
-GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (19 preceding siblings ...)
2021-11-09 5:51 ` [PULL 20/54] target/ppc: Move d{add, sub, mul, div, iex}[q] " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] " David Gibson
` (33 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, Luis Pires, qemu-ppc, qemu-devel, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
dcmpu: DFP Compare Unordered
dcmpuq: DFP Compare Unordered Quad
dcmpo: DFP Compare Ordered
dcmpoq: DFP Compare Ordered Quad
dtstex: DFP Test Exponent
dtstexq: DFP Test Exponent Quad
dtstsf: DFP Test Significance
dtstsfq: DFP Test Significance Quad
dtstsfi: DFP Test Significance Immediate
dtstsfiq: DFP Test Significance Immediate Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-12-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 20 ++++----
target/ppc/helper.h | 20 ++++----
target/ppc/insn32.decode | 29 +++++++++++
target/ppc/translate/dfp-impl.c.inc | 74 +++++++++++++----------------
target/ppc/translate/dfp-ops.c.inc | 31 ------------
5 files changed, 83 insertions(+), 91 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index da8eaaaff1..9be6809b33 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -507,8 +507,8 @@ static void CMPU_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXSNAN(dfp);
}
-DFP_HELPER_BF_AB(dcmpu, decNumberCompare, CMPU_PPs, 64)
-DFP_HELPER_BF_AB(dcmpuq, decNumberCompare, CMPU_PPs, 128)
+DFP_HELPER_BF_AB(DCMPU, decNumberCompare, CMPU_PPs, 64)
+DFP_HELPER_BF_AB(DCMPUQ, decNumberCompare, CMPU_PPs, 128)
static void CMPO_PPs(struct PPC_DFP *dfp)
{
@@ -518,8 +518,8 @@ static void CMPO_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXVC(dfp);
}
-DFP_HELPER_BF_AB(dcmpo, decNumberCompare, CMPO_PPs, 64)
-DFP_HELPER_BF_AB(dcmpoq, decNumberCompare, CMPO_PPs, 128)
+DFP_HELPER_BF_AB(DCMPO, decNumberCompare, CMPO_PPs, 64)
+DFP_HELPER_BF_AB(DCMPOQ, decNumberCompare, CMPO_PPs, 128)
#define DFP_HELPER_TSTDC(op, size) \
uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, uint32_t dcm) \
@@ -633,8 +633,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, ppc_fprp_t *b) \
return dfp.crbf; \
}
-DFP_HELPER_TSTEX(dtstex, 64)
-DFP_HELPER_TSTEX(dtstexq, 128)
+DFP_HELPER_TSTEX(DTSTEX, 64)
+DFP_HELPER_TSTEX(DTSTEXQ, 128)
#define DFP_HELPER_TSTSF(op, size) \
uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, ppc_fprp_t *b) \
@@ -670,8 +670,8 @@ uint32_t helper_##op(CPUPPCState *env, ppc_fprp_t *a, ppc_fprp_t *b) \
return dfp.crbf; \
}
-DFP_HELPER_TSTSF(dtstsf, 64)
-DFP_HELPER_TSTSF(dtstsfq, 128)
+DFP_HELPER_TSTSF(DTSTSF, 64)
+DFP_HELPER_TSTSF(DTSTSFQ, 128)
#define DFP_HELPER_TSTSFI(op, size) \
uint32_t helper_##op(CPUPPCState *env, uint32_t a, ppc_fprp_t *b) \
@@ -705,8 +705,8 @@ uint32_t helper_##op(CPUPPCState *env, uint32_t a, ppc_fprp_t *b) \
return dfp.crbf; \
}
-DFP_HELPER_TSTSFI(dtstsfi, 64)
-DFP_HELPER_TSTSFI(dtstsfiq, 128)
+DFP_HELPER_TSTSFI(DTSTSFI, 64)
+DFP_HELPER_TSTSFI(DTSTSFIQ, 128)
static void QUA_PPs(struct PPC_DFP *dfp)
{
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f802392614..a21c04ecf1 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -706,20 +706,20 @@ DEF_HELPER_4(DMUL, void, env, fprp, fprp, fprp)
DEF_HELPER_4(DMULQ, void, env, fprp, fprp, fprp)
DEF_HELPER_4(DDIV, void, env, fprp, fprp, fprp)
DEF_HELPER_4(DDIVQ, void, env, fprp, fprp, fprp)
-DEF_HELPER_3(dcmpo, i32, env, fprp, fprp)
-DEF_HELPER_3(dcmpoq, i32, env, fprp, fprp)
-DEF_HELPER_3(dcmpu, i32, env, fprp, fprp)
-DEF_HELPER_3(dcmpuq, i32, env, fprp, fprp)
+DEF_HELPER_3(DCMPO, i32, env, fprp, fprp)
+DEF_HELPER_3(DCMPOQ, i32, env, fprp, fprp)
+DEF_HELPER_3(DCMPU, i32, env, fprp, fprp)
+DEF_HELPER_3(DCMPUQ, i32, env, fprp, fprp)
DEF_HELPER_3(DTSTDC, i32, env, fprp, i32)
DEF_HELPER_3(DTSTDCQ, i32, env, fprp, i32)
DEF_HELPER_3(DTSTDG, i32, env, fprp, i32)
DEF_HELPER_3(DTSTDGQ, i32, env, fprp, i32)
-DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
-DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
-DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
-DEF_HELPER_3(dtstsfq, i32, env, fprp, fprp)
-DEF_HELPER_3(dtstsfi, i32, env, i32, fprp)
-DEF_HELPER_3(dtstsfiq, i32, env, i32, fprp)
+DEF_HELPER_3(DTSTEX, i32, env, fprp, fprp)
+DEF_HELPER_3(DTSTEXQ, i32, env, fprp, fprp)
+DEF_HELPER_3(DTSTSF, i32, env, fprp, fprp)
+DEF_HELPER_3(DTSTSFQ, i32, env, fprp, fprp)
+DEF_HELPER_3(DTSTSFI, i32, env, i32, fprp)
+DEF_HELPER_3(DTSTSFIQ, i32, env, i32, fprp)
DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index bb3322dc00..263911d358 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -57,6 +57,18 @@
&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+&X_bf bf ra rb
+@X_bf ...... bf:3 .. ra:5 rb:5 .......... . &X_bf
+
+@X_bf_ap_bp ...... bf:3 .. ....0 ....0 .......... . &X_bf ra=%x_frap rb=%x_frbp
+
+@X_bf_a_bp ...... bf:3 .. ra:5 ....0 .......... . &X_bf rb=%x_frbp
+
+&X_bf_uim bf uim rb
+@X_bf_uim ...... bf:3 . uim:6 rb:5 .......... . &X_bf_uim
+
+@X_bf_uim_bp ...... bf:3 . uim:6 ....0 .......... . &X_bf_uim rb=%x_frbp
+
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
@@ -196,6 +208,14 @@ DMULQ 111111 ..... ..... ..... 0000100010 . @X_tp_ap_bp_rc
DDIV 111011 ..... ..... ..... 1000100010 . @X_rc
DDIVQ 111111 ..... ..... ..... 1000100010 . @X_tp_ap_bp_rc
+### Decimal Floating-Point Compare Instructions
+
+DCMPU 111011 ... -- ..... ..... 1010000010 - @X_bf
+DCMPUQ 111111 ... -- ..... ..... 1010000010 - @X_bf_ap_bp
+
+DCMPO 111011 ... -- ..... ..... 0010000010 - @X_bf
+DCMPOQ 111111 ... -- ..... ..... 0010000010 - @X_bf_ap_bp
+
### Decimal Floating-Point Test Instructions
DTSTDC 111011 ... -- ..... ...... 011000010 - @Z22_bf_fra
@@ -204,6 +224,15 @@ DTSTDCQ 111111 ... -- ..... ...... 011000010 - @Z22_bf_frap
DTSTDG 111011 ... -- ..... ...... 011100010 - @Z22_bf_fra
DTSTDGQ 111111 ... -- ..... ...... 011100010 - @Z22_bf_frap
+DTSTEX 111011 ... -- ..... ..... 0010100010 - @X_bf
+DTSTEXQ 111111 ... -- ..... ..... 0010100010 - @X_bf_ap_bp
+
+DTSTSF 111011 ... -- ..... ..... 1010100010 - @X_bf
+DTSTSFQ 111111 ... -- ..... ..... 1010100010 - @X_bf_a_bp
+
+DTSTSFI 111011 ... - ...... ..... 1010100011 - @X_bf_uim
+DTSTSFIQ 111111 ... - ...... ..... 1010100011 - @X_bf_uim_bp
+
### Decimal Floating-Point Conversion Instructions
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index b08b38355b..d8dcc4c807 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -26,37 +26,32 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
return true; \
}
-#define GEN_DFP_BF_A_B(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr ra, rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
- cpu_env, ra, rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_ptr(rb); \
+#define TRANS_DFP_BF_A_B(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr ra, rb; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ ra = gen_fprp_ptr(a->ra); \
+ rb = gen_fprp_ptr(a->rb); \
+ gen_helper_##NAME(cpu_crf[a->bf], \
+ cpu_env, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ return true; \
}
-#define GEN_DFP_BF_I_B(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_i32 uim; \
- TCGv_ptr rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- uim = tcg_const_i32(UIMM5(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
- cpu_env, uim, rb); \
- tcg_temp_free_i32(uim); \
- tcg_temp_free_ptr(rb); \
+#define TRANS_DFP_BF_I_B(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr rb; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ rb = gen_fprp_ptr(a->rb); \
+ gen_helper_##NAME(cpu_crf[a->bf], \
+ cpu_env, tcg_constant_i32(a->uim), rb);\
+ tcg_temp_free_ptr(rb); \
+ return true; \
}
#define TRANS_DFP_BF_A_DCM(NAME) \
@@ -165,20 +160,20 @@ TRANS_DFP_T_A_B_Rc(DMUL)
TRANS_DFP_T_A_B_Rc(DMULQ)
TRANS_DFP_T_A_B_Rc(DDIV)
TRANS_DFP_T_A_B_Rc(DDIVQ)
-GEN_DFP_BF_A_B(dcmpu)
-GEN_DFP_BF_A_B(dcmpuq)
-GEN_DFP_BF_A_B(dcmpo)
-GEN_DFP_BF_A_B(dcmpoq)
+TRANS_DFP_BF_A_B(DCMPU)
+TRANS_DFP_BF_A_B(DCMPUQ)
+TRANS_DFP_BF_A_B(DCMPO)
+TRANS_DFP_BF_A_B(DCMPOQ)
TRANS_DFP_BF_A_DCM(DTSTDC)
TRANS_DFP_BF_A_DCM(DTSTDCQ)
TRANS_DFP_BF_A_DCM(DTSTDG)
TRANS_DFP_BF_A_DCM(DTSTDGQ)
-GEN_DFP_BF_A_B(dtstex)
-GEN_DFP_BF_A_B(dtstexq)
-GEN_DFP_BF_A_B(dtstsf)
-GEN_DFP_BF_A_B(dtstsfq)
-GEN_DFP_BF_I_B(dtstsfi)
-GEN_DFP_BF_I_B(dtstsfiq)
+TRANS_DFP_BF_A_B(DTSTEX)
+TRANS_DFP_BF_A_B(DTSTEXQ)
+TRANS_DFP_BF_A_B(DTSTSF)
+TRANS_DFP_BF_A_B(DTSTSFQ)
+TRANS_DFP_BF_I_B(DTSTSFI)
+TRANS_DFP_BF_I_B(DTSTSFIQ)
GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
@@ -210,7 +205,6 @@ GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-#undef GEN_DFP_BF_A_B
#undef GEN_DFP_T_B_U32_U32_Rc
#undef GEN_DFP_T_A_B_I32_Rc
#undef GEN_DFP_T_B_Rc
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index 38ea551488..e59425c8b2 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -1,9 +1,6 @@
#define _GEN_DFP_LONG(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
-#define _GEN_DFP_LONG_300(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_ISA300)
-
#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
@@ -17,9 +14,6 @@ GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
#define _GEN_DFP_QUAD(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
-#define _GEN_DFP_QUAD_300(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_ISA300)
-
#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
@@ -42,21 +36,6 @@ _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
-#define GEN_DFP_BF_A_B(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x00000001)
-
-#define GEN_DFP_BF_A_B_300(name, op1, op2) \
-_GEN_DFP_LONG_300(name, op1, op2, 0x00400001)
-
-#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
-
-#define GEN_DFP_BF_A_Bp(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
-
-#define GEN_DFP_BF_A_Bp_300(name, op1, op2) \
-_GEN_DFP_QUAD_300(name, op1, op2, 0x00400001)
-
#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
@@ -96,16 +75,6 @@ _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
-GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
-GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
-GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
-GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
-GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
-GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
-GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
-GEN_DFP_BF_A_B_300(dtstsfi, 0x03, 0x15),
-GEN_DFP_BF_A_Bp_300(dtstsfiq, 0x03, 0x15),
GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (20 preceding siblings ...)
2021-11-09 5:51 ` [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] " David Gibson
` (32 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, qemu-ppc, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
dquai: DFP Quantize Immediate
dquaiq: DFP Quantize Immediate Quad
drintx: DFP Round to FP Integer With Inexact
drintxq: DFP Round to FP Integer With Inexact Quad
drintn: DFP Round to FP Integer Without Inexact
drintnq: DFP Round to FP Integer Without Inexact Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-13-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 12 +++----
target/ppc/helper.h | 12 +++----
target/ppc/insn32.decode | 23 +++++++++++++
target/ppc/translate/dfp-impl.c.inc | 51 +++++++++++++----------------
target/ppc/translate/dfp-ops.c.inc | 18 ----------
5 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 9be6809b33..df3e6c7cb1 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -751,8 +751,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_QUAI(dquai, 64)
-DFP_HELPER_QUAI(dquaiq, 128)
+DFP_HELPER_QUAI(DQUAI, 64)
+DFP_HELPER_QUAI(DQUAIQ, 128)
#define DFP_HELPER_QUA(op, size) \
void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a, \
@@ -873,8 +873,8 @@ static void RINTX_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXSNAN(dfp);
}
-DFP_HELPER_RINT(drintx, RINTX_PPs, 64)
-DFP_HELPER_RINT(drintxq, RINTX_PPs, 128)
+DFP_HELPER_RINT(DRINTX, RINTX_PPs, 64)
+DFP_HELPER_RINT(DRINTXQ, RINTX_PPs, 128)
static void RINTN_PPs(struct PPC_DFP *dfp)
{
@@ -882,8 +882,8 @@ static void RINTN_PPs(struct PPC_DFP *dfp)
dfp_check_for_VXSNAN(dfp);
}
-DFP_HELPER_RINT(drintn, RINTN_PPs, 64)
-DFP_HELPER_RINT(drintnq, RINTN_PPs, 128)
+DFP_HELPER_RINT(DRINTN, RINTN_PPs, 64)
+DFP_HELPER_RINT(DRINTNQ, RINTN_PPs, 128)
void helper_dctdp(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
{
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index a21c04ecf1..70bc8ac579 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -720,16 +720,16 @@ DEF_HELPER_3(DTSTSF, i32, env, fprp, fprp)
DEF_HELPER_3(DTSTSFQ, i32, env, fprp, fprp)
DEF_HELPER_3(DTSTSFI, i32, env, i32, fprp)
DEF_HELPER_3(DTSTSFIQ, i32, env, i32, fprp)
-DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(DQUAI, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(DQUAIQ, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(drintx, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_5(drintxq, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_5(drintn, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_5(drintnq, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(DRINTX, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(DRINTXQ, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(DRINTN, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(DRINTNQ, void, env, fprp, fprp, i32, i32)
DEF_HELPER_3(dctdp, void, env, fprp, fprp)
DEF_HELPER_3(dctqpq, void, env, fprp, fprp)
DEF_HELPER_3(drsp, void, env, fprp, fprp)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 263911d358..5369af17b6 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -84,6 +84,18 @@
%z22_frap 17:4 !function=times_2
@Z22_bf_frap ...... bf:3 .. ....0 dm:6 ......... . &Z22_bf_fra fra=%z22_frap
+&Z23_tb frt frb r:bool rmc rc:bool
+@Z23_tb ...... frt:5 .... r:1 frb:5 rmc:2 ........ rc:1 &Z23_tb
+
+%z23_frtp 22:4 !function=times_2
+%z23_frbp 12:4 !function=times_2
+@Z23_tbp ...... ....0 .... r:1 ....0 rmc:2 ........ rc:1 &Z23_tb frt=%z23_frtp frb=%z23_frbp
+
+&Z23_te_tb te frt frb rmc rc:bool
+@Z23_te_tb ...... frt:5 te:5 frb:5 rmc:2 ........ rc:1 &Z23_te_tb
+
+@Z23_te_tbp ...... ....0 te:5 ....0 rmc:2 ........ rc:1 &Z23_te_tb frt=%z23_frtp frb=%z23_frbp
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -233,6 +245,17 @@ DTSTSFQ 111111 ... -- ..... ..... 1010100010 - @X_bf_a_bp
DTSTSFI 111011 ... - ...... ..... 1010100011 - @X_bf_uim
DTSTSFIQ 111111 ... - ...... ..... 1010100011 - @X_bf_uim_bp
+### Decimal Floating-Point Quantum Adjustment Instructions
+
+DQUAI 111011 ..... ..... ..... .. 01000011 . @Z23_te_tb
+DQUAIQ 111111 ..... ..... ..... .. 01000011 . @Z23_te_tbp
+
+DRINTX 111011 ..... ---- . ..... .. 01100011 . @Z23_tb
+DRINTXQ 111111 ..... ---- . ..... .. 01100011 . @Z23_tbp
+
+DRINTN 111011 ..... ---- . ..... .. 11100011 . @Z23_tb
+DRINTNQ 111111 ..... ---- . ..... .. 11100011 . @Z23_tbp
+
### Decimal Floating-Point Conversion Instructions
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index d8dcc4c807..cb481d028a 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -67,27 +67,23 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
return true; \
}
-#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, rb; \
- TCGv_i32 u32_1, u32_2; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
- u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_i32(u32_1); \
- tcg_temp_free_i32(u32_2); \
+#define TRANS_DFP_T_B_U32_U32_Rc(NAME, U32F1, U32F2) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr rt, rb; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ rt = gen_fprp_ptr(a->frt); \
+ rb = gen_fprp_ptr(a->frb); \
+ gen_helper_##NAME(cpu_env, rt, rb, \
+ tcg_constant_i32(a->U32F1), \
+ tcg_constant_i32(a->U32F2)); \
+ if (unlikely(a->rc)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rb); \
+ return true; \
}
#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
@@ -174,16 +170,16 @@ TRANS_DFP_BF_A_B(DTSTSF)
TRANS_DFP_BF_A_B(DTSTSFQ)
TRANS_DFP_BF_I_B(DTSTSFI)
TRANS_DFP_BF_I_B(DTSTSFIQ)
-GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
-GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
+TRANS_DFP_T_B_U32_U32_Rc(DQUAI, te, rmc)
+TRANS_DFP_T_B_U32_U32_Rc(DQUAIQ, te, rmc)
GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
-GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
+TRANS_DFP_T_B_U32_U32_Rc(DRINTX, r, rmc)
+TRANS_DFP_T_B_U32_U32_Rc(DRINTXQ, r, rmc)
+TRANS_DFP_T_B_U32_U32_Rc(DRINTN, r, rmc)
+TRANS_DFP_T_B_U32_U32_Rc(DRINTNQ, r, rmc)
GEN_DFP_T_B_Rc(dctdp)
GEN_DFP_T_B_Rc(dctqpq)
GEN_DFP_T_B_Rc(drsp)
@@ -205,7 +201,6 @@ GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-#undef GEN_DFP_T_B_U32_U32_Rc
#undef GEN_DFP_T_A_B_I32_Rc
#undef GEN_DFP_T_B_Rc
#undef GEN_DFP_T_FPR_I32_Rc
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index e59425c8b2..c563f84a0b 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -45,18 +45,6 @@ _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
-#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
-
-#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
-
-#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
-
#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
_GEN_DFP_LONG(name, op1, op2, 0x00070000)
@@ -75,16 +63,10 @@ _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
-GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
-GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
-GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
-GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
-GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (21 preceding siblings ...)
2021-11-09 5:51 ` [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] " David Gibson
` (31 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, qemu-ppc, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
dqua: DFP Quantize
dquaq: DFP Quantize Quad
drrnd: DFP Reround
drrndq: DFP Reround Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-14-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 8 ++---
target/ppc/helper.h | 8 ++---
target/ppc/insn32.decode | 18 +++++++++--
target/ppc/translate/dfp-impl.c.inc | 50 +++++++++++++----------------
target/ppc/translate/dfp-ops.c.inc | 25 ---------------
5 files changed, 47 insertions(+), 62 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index df3e6c7cb1..a50a73d3c0 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -769,8 +769,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_QUA(dqua, 64)
-DFP_HELPER_QUA(dquaq, 128)
+DFP_HELPER_QUA(DQUA, 64)
+DFP_HELPER_QUA(DQUAQ, 128)
static void _dfp_reround(uint8_t rmc, int32_t ref_sig, int32_t xmax,
struct PPC_DFP *dfp)
@@ -847,8 +847,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_RRND(drrnd, 64)
-DFP_HELPER_RRND(drrndq, 128)
+DFP_HELPER_RRND(DRRND, 64)
+DFP_HELPER_RRND(DRRNDQ, 128)
#define DFP_HELPER_RINT(op, postprocs, size) \
void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 70bc8ac579..70aebdfeff 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -722,10 +722,10 @@ DEF_HELPER_3(DTSTSFI, i32, env, i32, fprp)
DEF_HELPER_3(DTSTSFIQ, i32, env, i32, fprp)
DEF_HELPER_5(DQUAI, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(DQUAIQ, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
-DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DQUA, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DQUAQ, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DRRND, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(DRRNDQ, void, env, fprp, fprp, fprp, i32)
DEF_HELPER_5(DRINTX, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(DRINTXQ, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(DRINTN, void, env, fprp, fprp, i32, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 5369af17b6..f7c8d50bd9 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -84,11 +84,19 @@
%z22_frap 17:4 !function=times_2
@Z22_bf_frap ...... bf:3 .. ....0 dm:6 ......... . &Z22_bf_fra fra=%z22_frap
-&Z23_tb frt frb r:bool rmc rc:bool
-@Z23_tb ...... frt:5 .... r:1 frb:5 rmc:2 ........ rc:1 &Z23_tb
+&Z23_tab frt fra frb rmc rc:bool
+@Z23_tab ...... frt:5 fra:5 frb:5 rmc:2 ........ rc:1 &Z23_tab
%z23_frtp 22:4 !function=times_2
+%z23_frap 17:4 !function=times_2
%z23_frbp 12:4 !function=times_2
+@Z23_tabp ...... ....0 ....0 ....0 rmc:2 ........ rc:1 &Z23_tab frt=%z23_frtp fra=%z23_frap frb=%z23_frbp
+
+@Z23_tp_a_bp ...... ....0 fra:5 ....0 rmc:2 ........ rc:1 &Z23_tab frt=%z23_frtp frb=%z23_frbp
+
+&Z23_tb frt frb r:bool rmc rc:bool
+@Z23_tb ...... frt:5 .... r:1 frb:5 rmc:2 ........ rc:1 &Z23_tb
+
@Z23_tbp ...... ....0 .... r:1 ....0 rmc:2 ........ rc:1 &Z23_tb frt=%z23_frtp frb=%z23_frbp
&Z23_te_tb te frt frb rmc rc:bool
@@ -250,6 +258,12 @@ DTSTSFIQ 111111 ... - ...... ..... 1010100011 - @X_bf_uim_bp
DQUAI 111011 ..... ..... ..... .. 01000011 . @Z23_te_tb
DQUAIQ 111111 ..... ..... ..... .. 01000011 . @Z23_te_tbp
+DQUA 111011 ..... ..... ..... .. 00000011 . @Z23_tab
+DQUAQ 111111 ..... ..... ..... .. 00000011 . @Z23_tabp
+
+DRRND 111011 ..... ..... ..... .. 00100011 . @Z23_tab
+DRRNDQ 111111 ..... ..... ..... .. 00100011 . @Z23_tp_a_bp
+
DRINTX 111011 ..... ---- . ..... .. 01100011 . @Z23_tb
DRINTXQ 111111 ..... ---- . ..... .. 01100011 . @Z23_tbp
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index cb481d028a..30d65ffb46 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -86,28 +86,25 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
return true; \
}
-#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, ra, rb; \
- TCGv_i32 i32; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- ra = gen_fprp_ptr(rA(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- i32 = tcg_const_i32(i32fld(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, ra, rb, i32); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(ra); \
- tcg_temp_free_i32(i32); \
- }
+#define TRANS_DFP_T_A_B_I32_Rc(NAME, I32FLD) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr rt, ra, rb; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ rt = gen_fprp_ptr(a->frt); \
+ ra = gen_fprp_ptr(a->fra); \
+ rb = gen_fprp_ptr(a->frb); \
+ gen_helper_##NAME(cpu_env, rt, ra, rb, \
+ tcg_constant_i32(a->I32FLD)); \
+ if (unlikely(a->rc)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ return true; \
+}
#define GEN_DFP_T_B_Rc(name) \
static void gen_##name(DisasContext *ctx) \
@@ -172,10 +169,10 @@ TRANS_DFP_BF_I_B(DTSTSFI)
TRANS_DFP_BF_I_B(DTSTSFIQ)
TRANS_DFP_T_B_U32_U32_Rc(DQUAI, te, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DQUAIQ, te, rmc)
-GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
-GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
-GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
-GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
+TRANS_DFP_T_A_B_I32_Rc(DQUA, rmc)
+TRANS_DFP_T_A_B_I32_Rc(DQUAQ, rmc)
+TRANS_DFP_T_A_B_I32_Rc(DRRND, rmc)
+TRANS_DFP_T_A_B_I32_Rc(DRRNDQ, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DRINTX, r, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DRINTXQ, r, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DRINTN, r, rmc)
@@ -201,7 +198,6 @@ GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-#undef GEN_DFP_T_A_B_I32_Rc
#undef GEN_DFP_T_B_Rc
#undef GEN_DFP_T_FPR_I32_Rc
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index c563f84a0b..3e0dfae796 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -5,12 +5,6 @@ GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-
#define _GEN_DFP_QUAD(name, op1, op2, mask) \
GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
@@ -18,12 +12,6 @@ GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
-
#define GEN_DFP_T_B_Rc(name, op1, op2) \
_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
@@ -36,15 +24,6 @@ _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
-#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
-_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
-
-#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
-_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
-
#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
_GEN_DFP_LONG(name, op1, op2, 0x00070000)
@@ -63,10 +42,6 @@ _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
-GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
-GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
-GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (22 preceding siblings ...)
2021-11-09 5:51 ` [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] " David Gibson
` (30 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, qemu-ppc, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
dctdp: DFP Convert To DFP Long
dctqpq: DFP Convert To DFP Extended
drsp: DFP Round To DFP Short
drdpq: DFP Round To DFP Long
dcffix: DFP Convert From Fixed
dcffixq: DFP Convert From Fixed Quad
dctfix: DFP Convert To Fixed
dctfixq: DFP Convert To Fixed Quad
dxex: DFP Extract Biased Exponent
dxexq: DFP Extract Biased Exponent Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-15-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 20 +++++------
target/ppc/helper.h | 20 +++++------
target/ppc/insn32.decode | 23 ++++++++++++
target/ppc/translate/dfp-impl.c.inc | 54 ++++++++++++++---------------
target/ppc/translate/dfp-ops.c.inc | 22 ------------
5 files changed, 69 insertions(+), 70 deletions(-)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index a50a73d3c0..d950d0d3fc 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -885,7 +885,7 @@ static void RINTN_PPs(struct PPC_DFP *dfp)
DFP_HELPER_RINT(DRINTN, RINTN_PPs, 64)
DFP_HELPER_RINT(DRINTNQ, RINTN_PPs, 128)
-void helper_dctdp(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
+void helper_DCTDP(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
{
struct PPC_DFP dfp;
ppc_vsr_t vb;
@@ -901,7 +901,7 @@ void helper_dctdp(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
dfp_set_FPRF_from_FRT(&dfp);
}
-void helper_dctqpq(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
+void helper_DCTQPQ(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
{
struct PPC_DFP dfp;
ppc_vsr_t vb;
@@ -916,7 +916,7 @@ void helper_dctqpq(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
set_dfp128(t, &dfp.vt);
}
-void helper_drsp(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
+void helper_DRSP(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
{
struct PPC_DFP dfp;
uint32_t t_short = 0;
@@ -934,7 +934,7 @@ void helper_drsp(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
set_dfp64(t, &vt);
}
-void helper_drdpq(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
+void helper_DRDPQ(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b)
{
struct PPC_DFP dfp;
dfp_prepare_decimal128(&dfp, 0, b, env);
@@ -972,8 +972,8 @@ static void CFFIX_PPs(struct PPC_DFP *dfp)
dfp_check_for_XX(dfp);
}
-DFP_HELPER_CFFIX(dcffix, 64)
-DFP_HELPER_CFFIX(dcffixq, 128)
+DFP_HELPER_CFFIX(DCFFIX, 64)
+DFP_HELPER_CFFIX(DCFFIXQ, 128)
void helper_DCFFIXQQ(CPUPPCState *env, ppc_fprp_t *t, ppc_avr_t *b)
{
@@ -1022,8 +1022,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
set_dfp64(t, &dfp.vt); \
}
-DFP_HELPER_CTFIX(dctfix, 64)
-DFP_HELPER_CTFIX(dctfixq, 128)
+DFP_HELPER_CTFIX(DCTFIX, 64)
+DFP_HELPER_CTFIX(DCTFIXQ, 128)
void helper_DCTFIXQQ(CPUPPCState *env, ppc_avr_t *t, ppc_fprp_t *b)
{
@@ -1233,8 +1233,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
} \
}
-DFP_HELPER_XEX(dxex, 64)
-DFP_HELPER_XEX(dxexq, 128)
+DFP_HELPER_XEX(DXEX, 64)
+DFP_HELPER_XEX(DXEXQ, 128)
static void dfp_set_raw_exp_64(ppc_vsr_t *t, uint64_t raw)
{
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 70aebdfeff..b302928a78 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -730,22 +730,22 @@ DEF_HELPER_5(DRINTX, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(DRINTXQ, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(DRINTN, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(DRINTNQ, void, env, fprp, fprp, i32, i32)
-DEF_HELPER_3(dctdp, void, env, fprp, fprp)
-DEF_HELPER_3(dctqpq, void, env, fprp, fprp)
-DEF_HELPER_3(drsp, void, env, fprp, fprp)
-DEF_HELPER_3(drdpq, void, env, fprp, fprp)
-DEF_HELPER_3(dcffix, void, env, fprp, fprp)
-DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
+DEF_HELPER_3(DCTDP, void, env, fprp, fprp)
+DEF_HELPER_3(DCTQPQ, void, env, fprp, fprp)
+DEF_HELPER_3(DRSP, void, env, fprp, fprp)
+DEF_HELPER_3(DRDPQ, void, env, fprp, fprp)
+DEF_HELPER_3(DCFFIX, void, env, fprp, fprp)
+DEF_HELPER_3(DCFFIXQ, void, env, fprp, fprp)
DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
-DEF_HELPER_3(dctfix, void, env, fprp, fprp)
-DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
+DEF_HELPER_3(DCTFIX, void, env, fprp, fprp)
+DEF_HELPER_3(DCTFIXQ, void, env, fprp, fprp)
DEF_HELPER_3(DCTFIXQQ, void, env, avr, fprp)
DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
DEF_HELPER_4(ddedpdq, void, env, fprp, fprp, i32)
DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32)
DEF_HELPER_4(denbcdq, void, env, fprp, fprp, i32)
-DEF_HELPER_3(dxex, void, env, fprp, fprp)
-DEF_HELPER_3(dxexq, void, env, fprp, fprp)
+DEF_HELPER_3(DXEX, void, env, fprp, fprp)
+DEF_HELPER_3(DXEXQ, void, env, fprp, fprp)
DEF_HELPER_4(DIEX, void, env, fprp, fprp, fprp)
DEF_HELPER_4(DIEXQ, void, env, fprp, fprp, fprp)
DEF_HELPER_4(dscri, void, env, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f7c8d50bd9..033bae2b32 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -54,6 +54,15 @@
@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
+&X_tb_rc rt rb rc:bool
+@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc
+
+@X_tbp_rc ...... ....0 ..... ....0 .......... rc:1 &X_tb_rc rt=%x_frtp rb=%x_frbp
+
+@X_tp_b_rc ...... ....0 ..... rb:5 .......... rc:1 &X_tb_rc rt=%x_frtp
+
+@X_t_bp_rc ...... rt:5 ..... ....0 .......... rc:1 &X_tb_rc rb=%x_frbp
+
&X_bi rt bi
@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
@@ -272,11 +281,25 @@ DRINTNQ 111111 ..... ---- . ..... .. 11100011 . @Z23_tbp
### Decimal Floating-Point Conversion Instructions
+DCTDP 111011 ..... ----- ..... 0100000010 . @X_tb_rc
+DCTQPQ 111111 ..... ----- ..... 0100000010 . @X_tp_b_rc
+
+DRSP 111011 ..... ----- ..... 1100000010 . @X_tb_rc
+DRDPQ 111111 ..... ----- ..... 1100000010 . @X_tbp_rc
+
+DCFFIX 111011 ..... ----- ..... 1100100010 . @X_tb_rc
+DCFFIXQ 111111 ..... ----- ..... 1100100010 . @X_tp_b_rc
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
+
+DCTFIX 111011 ..... ----- ..... 0100100010 . @X_tb_rc
+DCTFIXQ 111111 ..... ----- ..... 0100100010 . @X_t_bp_rc
DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp
### Decimal Floating-Point Format Instructions
+DXEX 111011 ..... ----- ..... 0101100010 . @X_tb_rc
+DXEXQ 111111 ..... ----- ..... 0101100010 . @X_t_bp_rc
+
DIEX 111011 ..... ..... ..... 1101100010 . @X_rc
DIEXQ 111111 ..... ..... ..... 1101100010 . @X_tp_a_bp_rc
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 30d65ffb46..736292584c 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -106,23 +106,22 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
return true; \
}
-#define GEN_DFP_T_B_Rc(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, rb; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- rb = gen_fprp_ptr(rB(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, rb); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rb); \
- }
+#define TRANS_DFP_T_B_Rc(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr rt, rb; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ rt = gen_fprp_ptr(a->rt); \
+ rb = gen_fprp_ptr(a->rb); \
+ gen_helper_##NAME(cpu_env, rt, rb); \
+ if (unlikely(a->rc)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rb); \
+ return true; \
+}
#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
static void gen_##name(DisasContext *ctx) \
@@ -177,20 +176,20 @@ TRANS_DFP_T_B_U32_U32_Rc(DRINTX, r, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DRINTXQ, r, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DRINTN, r, rmc)
TRANS_DFP_T_B_U32_U32_Rc(DRINTNQ, r, rmc)
-GEN_DFP_T_B_Rc(dctdp)
-GEN_DFP_T_B_Rc(dctqpq)
-GEN_DFP_T_B_Rc(drsp)
-GEN_DFP_T_B_Rc(drdpq)
-GEN_DFP_T_B_Rc(dcffix)
-GEN_DFP_T_B_Rc(dcffixq)
-GEN_DFP_T_B_Rc(dctfix)
-GEN_DFP_T_B_Rc(dctfixq)
+TRANS_DFP_T_B_Rc(DCTDP)
+TRANS_DFP_T_B_Rc(DCTQPQ)
+TRANS_DFP_T_B_Rc(DRSP)
+TRANS_DFP_T_B_Rc(DRDPQ)
+TRANS_DFP_T_B_Rc(DCFFIX)
+TRANS_DFP_T_B_Rc(DCFFIXQ)
+TRANS_DFP_T_B_Rc(DCTFIX)
+TRANS_DFP_T_B_Rc(DCTFIXQ)
GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
-GEN_DFP_T_B_Rc(dxex)
-GEN_DFP_T_B_Rc(dxexq)
+TRANS_DFP_T_B_Rc(DXEX)
+TRANS_DFP_T_B_Rc(DXEXQ)
TRANS_DFP_T_A_B_Rc(DIEX)
TRANS_DFP_T_A_B_Rc(DIEXQ)
GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
@@ -198,7 +197,6 @@ GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-#undef GEN_DFP_T_B_Rc
#undef GEN_DFP_T_FPR_I32_Rc
static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
index 3e0dfae796..e29c4b2194 100644
--- a/target/ppc/translate/dfp-ops.c.inc
+++ b/target/ppc/translate/dfp-ops.c.inc
@@ -12,18 +12,6 @@ GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-#define GEN_DFP_T_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
-
-#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
-
-#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
-
-#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
-
#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
_GEN_DFP_LONG(name, op1, op2, 0x00070000)
@@ -42,20 +30,10 @@ _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
-GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
-GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
-GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
-GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
-GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
-GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
-GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
-GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
-GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (23 preceding siblings ...)
2021-11-09 5:51 ` [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents David Gibson
` (29 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Philippe Mathieu-Daudé,
Luis Pires, qemu-ppc, David Gibson
From: Luis Pires <luis.pires@eldorado.org.br>
Move the following instructions to decodetree:
ddedpd: DFP Decode DPD To BCD
ddedpdq: DFP Decode DPD To BCD Quad
denbcd: DFP Encode BCD To DPD
denbcdq: DFP Encode BCD To DPD Quad
dscli: DFP Shift Significand Left Immediate
dscliq: DFP Shift Significand Left Immediate Quad
dscri: DFP Shift Significand Right Immediate
dscriq: DFP Shift Significand Right Immediate Quad
Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were
moved to decodetree.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-16-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/dfp_helper.c | 16 ++++-----
target/ppc/helper.h | 16 ++++-----
target/ppc/insn32.decode | 28 +++++++++++++++
target/ppc/translate.c | 2 --
target/ppc/translate/dfp-impl.c.inc | 53 +++++++++++++----------------
target/ppc/translate/dfp-ops.c.inc | 40 ----------------------
6 files changed, 68 insertions(+), 87 deletions(-)
delete mode 100644 target/ppc/translate/dfp-ops.c.inc
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index d950d0d3fc..0d01ac3de0 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -1131,8 +1131,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_DEDPD(ddedpd, 64)
-DFP_HELPER_DEDPD(ddedpdq, 128)
+DFP_HELPER_DEDPD(DDEDPD, 64)
+DFP_HELPER_DEDPD(DDEDPDQ, 128)
static inline uint8_t dfp_get_bcd_digit_64(ppc_vsr_t *t, unsigned n)
{
@@ -1199,8 +1199,8 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_ENBCD(denbcd, 64)
-DFP_HELPER_ENBCD(denbcdq, 128)
+DFP_HELPER_ENBCD(DENBCD, 64)
+DFP_HELPER_ENBCD(DENBCDQ, 128)
#define DFP_HELPER_XEX(op, size) \
void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
@@ -1387,7 +1387,7 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *a, \
set_dfp##size(t, &dfp.vt); \
}
-DFP_HELPER_SHIFT(dscli, 64, 1)
-DFP_HELPER_SHIFT(dscliq, 128, 1)
-DFP_HELPER_SHIFT(dscri, 64, 0)
-DFP_HELPER_SHIFT(dscriq, 128, 0)
+DFP_HELPER_SHIFT(DSCLI, 64, 1)
+DFP_HELPER_SHIFT(DSCLIQ, 128, 1)
+DFP_HELPER_SHIFT(DSCRI, 64, 0)
+DFP_HELPER_SHIFT(DSCRIQ, 128, 0)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index b302928a78..72e66c5fe8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -740,18 +740,18 @@ DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
DEF_HELPER_3(DCTFIX, void, env, fprp, fprp)
DEF_HELPER_3(DCTFIXQ, void, env, fprp, fprp)
DEF_HELPER_3(DCTFIXQQ, void, env, avr, fprp)
-DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
-DEF_HELPER_4(ddedpdq, void, env, fprp, fprp, i32)
-DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32)
-DEF_HELPER_4(denbcdq, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DDEDPD, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DDEDPDQ, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DENBCD, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DENBCDQ, void, env, fprp, fprp, i32)
DEF_HELPER_3(DXEX, void, env, fprp, fprp)
DEF_HELPER_3(DXEXQ, void, env, fprp, fprp)
DEF_HELPER_4(DIEX, void, env, fprp, fprp, fprp)
DEF_HELPER_4(DIEXQ, void, env, fprp, fprp, fprp)
-DEF_HELPER_4(dscri, void, env, fprp, fprp, i32)
-DEF_HELPER_4(dscriq, void, env, fprp, fprp, i32)
-DEF_HELPER_4(dscli, void, env, fprp, fprp, i32)
-DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DSCRI, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DSCRIQ, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DSCLI, void, env, fprp, fprp, i32)
+DEF_HELPER_4(DSCLIQ, void, env, fprp, fprp, i32)
DEF_HELPER_1(tbegin, void, env)
DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 033bae2b32..65075f0d03 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -81,6 +81,16 @@
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+&X_tb_sp_rc rt rb sp rc:bool
+@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
+
+@X_tbp_sp_rc ...... ....0 sp:2 ... ....0 .......... rc:1 &X_tb_sp_rc rt=%x_frtp rb=%x_frbp
+
+&X_tb_s_rc rt rb s:bool rc:bool
+@X_tb_s_rc ...... rt:5 s:1 .... rb:5 .......... rc:1 &X_tb_s_rc
+
+@X_tbp_s_rc ...... ....0 s:1 .... ....0 .......... rc:1 &X_tb_s_rc rt=%x_frtp rb=%x_frbp
+
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -93,6 +103,12 @@
%z22_frap 17:4 !function=times_2
@Z22_bf_frap ...... bf:3 .. ....0 dm:6 ......... . &Z22_bf_fra fra=%z22_frap
+&Z22_ta_sh_rc rt ra sh rc:bool
+@Z22_ta_sh_rc ...... rt:5 ra:5 sh:6 ......... rc:1 &Z22_ta_sh_rc
+
+%z22_frtp 22:4 !function=times_2
+@Z22_tap_sh_rc ...... ....0 ....0 sh:6 ......... rc:1 &Z22_ta_sh_rc rt=%z22_frtp ra=%z22_frap
+
&Z23_tab frt fra frb rmc rc:bool
@Z23_tab ...... frt:5 fra:5 frb:5 rmc:2 ........ rc:1 &Z23_tab
@@ -297,12 +313,24 @@ DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp
### Decimal Floating-Point Format Instructions
+DDEDPD 111011 ..... .. --- ..... 0101000010 . @X_tb_sp_rc
+DDEDPDQ 111111 ..... .. --- ..... 0101000010 . @X_tbp_sp_rc
+
+DENBCD 111011 ..... . ---- ..... 1101000010 . @X_tb_s_rc
+DENBCDQ 111111 ..... . ---- ..... 1101000010 . @X_tbp_s_rc
+
DXEX 111011 ..... ----- ..... 0101100010 . @X_tb_rc
DXEXQ 111111 ..... ----- ..... 0101100010 . @X_t_bp_rc
DIEX 111011 ..... ..... ..... 1101100010 . @X_rc
DIEXQ 111111 ..... ..... ..... 1101100010 . @X_tp_a_bp_rc
+DSCLI 111011 ..... ..... ...... 001000010 . @Z22_ta_sh_rc
+DSCLIQ 111111 ..... ..... ...... 001000010 . @Z22_tap_sh_rc
+
+DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc
+DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 486339d402..659859ff5f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -8079,8 +8079,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
#include "translate/vsx-ops.c.inc"
-#include "translate/dfp-ops.c.inc"
-
#include "translate/spe-ops.c.inc"
};
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index 736292584c..f9f1d58d44 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -123,25 +123,22 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
return true; \
}
-#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv_ptr rt, rs; \
- TCGv_i32 i32; \
- if (unlikely(!ctx->fpu_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_FPU); \
- return; \
- } \
- rt = gen_fprp_ptr(rD(ctx->opcode)); \
- rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
- i32 = tcg_const_i32(i32fld(ctx->opcode)); \
- gen_helper_##name(cpu_env, rt, rs, i32); \
- if (unlikely(Rc(ctx->opcode) != 0)) { \
- gen_set_cr1_from_fpscr(ctx); \
- } \
- tcg_temp_free_ptr(rt); \
- tcg_temp_free_ptr(rs); \
- tcg_temp_free_i32(i32); \
+#define TRANS_DFP_T_FPR_I32_Rc(NAME, FPRFLD, I32FLD) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ TCGv_ptr rt, rx; \
+ REQUIRE_INSNS_FLAGS2(ctx, DFP); \
+ REQUIRE_FPU(ctx); \
+ rt = gen_fprp_ptr(a->rt); \
+ rx = gen_fprp_ptr(a->FPRFLD); \
+ gen_helper_##NAME(cpu_env, rt, rx, \
+ tcg_constant_i32(a->I32FLD)); \
+ if (unlikely(a->rc)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
+ tcg_temp_free_ptr(rt); \
+ tcg_temp_free_ptr(rx); \
+ return true; \
}
TRANS_DFP_T_A_B_Rc(DADD)
@@ -184,20 +181,18 @@ TRANS_DFP_T_B_Rc(DCFFIX)
TRANS_DFP_T_B_Rc(DCFFIXQ)
TRANS_DFP_T_B_Rc(DCTFIX)
TRANS_DFP_T_B_Rc(DCTFIXQ)
-GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
-GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
-GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
-GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
+TRANS_DFP_T_FPR_I32_Rc(DDEDPD, rb, sp)
+TRANS_DFP_T_FPR_I32_Rc(DDEDPDQ, rb, sp)
+TRANS_DFP_T_FPR_I32_Rc(DENBCD, rb, s)
+TRANS_DFP_T_FPR_I32_Rc(DENBCDQ, rb, s)
TRANS_DFP_T_B_Rc(DXEX)
TRANS_DFP_T_B_Rc(DXEXQ)
TRANS_DFP_T_A_B_Rc(DIEX)
TRANS_DFP_T_A_B_Rc(DIEXQ)
-GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
-GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
-GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
-GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
-
-#undef GEN_DFP_T_FPR_I32_Rc
+TRANS_DFP_T_FPR_I32_Rc(DSCLI, ra, sh)
+TRANS_DFP_T_FPR_I32_Rc(DSCLIQ, ra, sh)
+TRANS_DFP_T_FPR_I32_Rc(DSCRI, ra, sh)
+TRANS_DFP_T_FPR_I32_Rc(DSCRIQ, ra, sh)
static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
{
diff --git a/target/ppc/translate/dfp-ops.c.inc b/target/ppc/translate/dfp-ops.c.inc
deleted file mode 100644
index e29c4b2194..0000000000
--- a/target/ppc/translate/dfp-ops.c.inc
+++ /dev/null
@@ -1,40 +0,0 @@
-#define _GEN_DFP_LONG(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_QUAD(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
-
-#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
-GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
-GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
-
-#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x00070000)
-
-#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
-
-#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
-_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
-
-#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
-_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
-
-#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
-_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
-
-#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
-_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
-
-GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
-GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
-GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
-GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
-GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
-GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
-GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
-GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (24 preceding siblings ...)
2021-11-09 5:51 ` [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled David Gibson
` (28 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug; +Cc: qemu-ppc, qemu-devel, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Test is wrong and the backend can never updated. It could have led to
a QEMU crash but since the firmware deactivates flash access if a valid
layout is not detected, it went unnoticed.
Reported-by: Coverity CID 1465223
Fixes: 35dde5766211 ("ppc/pnv: Add a PNOR model")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211102162905.762078-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_pnor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c
index 5ef1cf2afb..83ecccca28 100644
--- a/hw/ppc/pnv_pnor.c
+++ b/hw/ppc/pnv_pnor.c
@@ -36,7 +36,7 @@ static void pnv_pnor_update(PnvPnor *s, int offset, int size)
int offset_end;
int ret;
- if (s->blk) {
+ if (!s->blk || !blk_is_writable(s->blk)) {
return;
}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (25 preceding siblings ...)
2021-11-09 5:51 ` [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc David Gibson
` (27 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, David Gibson, qemu-ppc, qemu-devel
From: BALATON Zoltan <balaton@eik.bme.hu>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20211101151023.F0D02748F5A@zero.eik.bme.hu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pegasos2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index e427ac2fe0..298e6b93e2 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -23,6 +23,7 @@
#include "hw/qdev-properties.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
+#include "sysemu/qtest.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/fw-path-provider.h"
@@ -199,7 +200,7 @@ static void pegasos2_init(MachineState *machine)
if (!pm->vof) {
warn_report("Option -kernel may be ineffective with -bios.");
}
- } else if (pm->vof) {
+ } else if (pm->vof && !qtest_enabled()) {
warn_report("Using Virtual OpenFirmware but no -kernel option.");
}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (26 preceding siblings ...)
2021-11-09 5:51 ` [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions David Gibson
` (26 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
There's no reason to keep vector-impl.c.inc separate from
vmx-impl.c.inc. Additionally, let GVec handle the multiple calls to
helper_cfuged for us.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-2-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 2 +-
target/ppc/int_helper.c | 2 +-
target/ppc/translate.c | 1 -
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
target/ppc/translate/vector-impl.c.inc | 48 ----------------------
target/ppc/translate/vmx-impl.c.inc | 16 ++++++++
6 files changed, 19 insertions(+), 52 deletions(-)
delete mode 100644 target/ppc/translate/vector-impl.c.inc
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 72e66c5fe8..401575b935 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,7 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
-DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 913d76be6e..f03c864e48 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -324,7 +324,7 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
-uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+uint64_t helper_CFUGED(uint64_t src, uint64_t mask)
{
/*
* Instead of processing the mask bit-by-bit from the most significant to
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 659859ff5f..fc9d35a7a8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7407,7 +7407,6 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
-#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 220b099fcd..fa519c2d3e 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -407,7 +407,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
- gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+ gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
deleted file mode 100644
index 197e903337..0000000000
--- a/target/ppc/translate/vector-impl.c.inc
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Power ISA decode for Vector Facility instructions
- *
- * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
-{
- TCGv_i64 tgt, src, mask;
-
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
- REQUIRE_VECTOR(ctx);
-
- tgt = tcg_temp_new_i64();
- src = tcg_temp_new_i64();
- mask = tcg_temp_new_i64();
-
- /* centrifuge lower double word */
- get_cpu_vsrl(src, a->vra + 32);
- get_cpu_vsrl(mask, a->vrb + 32);
- gen_helper_cfuged(tgt, src, mask);
- set_cpu_vsrl(a->vrt + 32, tgt);
-
- /* centrifuge higher double word */
- get_cpu_vsrh(src, a->vra + 32);
- get_cpu_vsrh(mask, a->vrb + 32);
- gen_helper_cfuged(tgt, src, mask);
- set_cpu_vsrh(a->vrt + 32, tgt);
-
- tcg_temp_free_i64(tgt);
- tcg_temp_free_i64(src);
- tcg_temp_free_i64(mask);
-
- return true;
-}
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 92b9527aff..e36c66589c 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1559,6 +1559,22 @@ GEN_VXFORM3(vpermxor, 22, 0xFF)
GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_CFUGED,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (27 preceding siblings ...)
2021-11-09 5:51 ` [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction David Gibson
` (25 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Matheus Ferst, David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
The signature of do_cntzdm is changed to allow reuse as GVecGen3i.fni8.
The method is also moved out of #ifdef TARGET_PPC64, as PowerISA doesn't
say vclzdm and vctzdm are 64-bit only.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-3-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/fixedpoint-impl.c.inc | 4 +--
target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++++
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 65075f0d03..6ce06b231d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -334,3 +334,5 @@ DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
+VCLZDM 000100 ..... ..... ..... 11110000100 @VX
+VCTZDM 000100 ..... ..... ..... 11111000100 @VX
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index fa519c2d3e..e093562e2a 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -414,8 +414,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
return true;
}
-#if defined(TARGET_PPC64)
-static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
+static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
{
TCGv_i64 tmp;
TCGLabel *l1;
@@ -444,7 +443,6 @@ static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
tcg_gen_mov_i64(dst, tmp);
}
-#endif
static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
{
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index e36c66589c..6da8a9123f 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1575,6 +1575,38 @@ static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3i g = {
+ .fni8 = do_cntzdm,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, false, &g);
+
+ return true;
+}
+
+static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3i g = {
+ .fni8 = do_cntzdm,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, true, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (28 preceding siblings ...)
2021-11-09 5:51 ` [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions David Gibson
` (24 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Matheus Ferst, David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
pdepd and pextd helpers are moved out of #ifdef (TARGET_PPC64) to allow
them to be reused as GVecGen3.fni8.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-4-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/int_helper.c | 2 --
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
4 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 401575b935..0e99f8095c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -47,9 +47,9 @@ DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6ce06b231d..4666c06f55 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -336,3 +336,5 @@ DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
VCLZDM 000100 ..... ..... ..... 11110000100 @VX
VCTZDM 000100 ..... ..... ..... 11111000100 @VX
+VPDEPD 000100 ..... ..... ..... 10111001101 @VX
+VPEXTD 000100 ..... ..... ..... 10110001101 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index f03c864e48..42541736f1 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -386,7 +386,6 @@ uint64_t helper_CFUGED(uint64_t src, uint64_t mask)
return left | (right >> n);
}
-#if defined(TARGET_PPC64)
uint64_t helper_PDEPD(uint64_t src, uint64_t mask)
{
int i, o;
@@ -422,7 +421,6 @@ uint64_t helper_PEXTD(uint64_t src, uint64_t mask)
return result;
}
-#endif
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6da8a9123f..cddb3848ab 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1607,6 +1607,38 @@ static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_PDEPD,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
+static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
+{
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_PEXTD,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (29 preceding siblings ...)
2021-11-09 5:51 ` [PULL 30/54] target/ppc: Implement vpdepd/vpextd instruction David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns David Gibson
` (23 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-5-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 8 ++++
target/ppc/translate/vmx-impl.c.inc | 66 +++++++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 4666c06f55..257b11113d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -38,6 +38,9 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+&VN vrt vra vrb sh
+@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
+
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@@ -338,3 +341,8 @@ VCLZDM 000100 ..... ..... ..... 11110000100 @VX
VCTZDM 000100 ..... ..... ..... 11111000100 @VX
VPDEPD 000100 ..... ..... ..... 10111001101 @VX
VPEXTD 000100 ..... ..... ..... 10110001101 @VX
+
+## Vector Permute and Formatting Instruction
+
+VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
+VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index cddb3848ab..6edffd5637 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1257,6 +1257,72 @@ static void gen_vsldoi(DisasContext *ctx)
tcg_temp_free_i32(sh);
}
+static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
+{
+ TCGv_i64 t0, t1, t2;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vra, true);
+ get_avr64(t1, a->vra, false);
+
+ if (a->sh != 0) {
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t2, a->vrb, true);
+
+ tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
+ tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
+
+ tcg_temp_free_i64(t2);
+ }
+
+ set_avr64(a->vrt, t0, true);
+ set_avr64(a->vrt, t1, false);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
+static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
+{
+ TCGv_i64 t2, t1, t0;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vrb, false);
+ get_avr64(t1, a->vrb, true);
+
+ if (a->sh != 0) {
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t2, a->vra, false);
+
+ tcg_gen_extract2_i64(t0, t0, t1, a->sh);
+ tcg_gen_extract2_i64(t1, t1, t2, a->sh);
+
+ tcg_temp_free_i64(t2);
+ }
+
+ set_avr64(a->vrt, t0, false);
+ set_avr64(a->vrt, t1, true);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (30 preceding siblings ...)
2021-11-09 5:51 ` [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns David Gibson
` (22 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsblx: Vector Insert Byte from GPR using GPR-specified Left-Index
vinshlx: Vector Insert Halfword from GPR using GPR-specified Left-Index
vinswlx: Vector Insert Word from GPR using GPR-specified Left-Index
vinsdlx: Vector Insert Doubleword from GPR using GPR-specified
Left-Index
vinsbrx: Vector Insert Byte from GPR using GPR-specified Right-Index
vinshrx: Vector Insert Halfword from GPR using GPR-specified
Right-Index
vinswrx: Vector Insert Word from GPR using GPR-specified Right-Index
vinsdrx: Vector Insert Doubleword from GPR using GPR-specified
Right-Index
The helpers and do_vinsx receive i64 to allow code sharing with the
future implementation of Vector Insert from VSR using GPR Index.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-6-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 4 +++
target/ppc/insn32.decode | 9 ++++++
target/ppc/int_helper.c | 30 +++++++++++++++++
target/ppc/translate/vmx-impl.c.inc | 50 +++++++++++++++++++++++++++++
4 files changed, 93 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0e99f8095c..80f88ce78b 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -228,6 +228,10 @@ DEF_HELPER_3(vinsertb, void, avr, avr, i32)
DEF_HELPER_3(vinserth, void, avr, avr, i32)
DEF_HELPER_3(vinsertw, void, avr, avr, i32)
DEF_HELPER_3(vinsertd, void, avr, avr, i32)
+DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
+DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
+DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
+DEF_HELPER_4(VINSDLX, void, env, avr, i64, tl)
DEF_HELPER_2(vextsb2w, void, avr, avr)
DEF_HELPER_2(vextsh2w, void, avr, avr)
DEF_HELPER_2(vextsb2d, void, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 257b11113d..b794424496 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -344,5 +344,14 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VINSBLX 000100 ..... ..... ..... 01000001111 @VX
+VINSBRX 000100 ..... ..... ..... 01100001111 @VX
+VINSHLX 000100 ..... ..... ..... 01001001111 @VX
+VINSHRX 000100 ..... ..... ..... 01101001111 @VX
+VINSWLX 000100 ..... ..... ..... 01010001111 @VX
+VINSWRX 000100 ..... ..... ..... 01110001111 @VX
+VINSDLX 000100 ..... ..... ..... 01011001111 @VX
+VINSDRX 000100 ..... ..... ..... 01111001111 @VX
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 42541736f1..80b7f8814f 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1632,6 +1632,36 @@ VINSERT(h, u16)
VINSERT(w, u32)
VINSERT(d, u64)
#undef VINSERT
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX])
+#else
+#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[15 - (IDX)] - (SIZE) + 1)
+#endif
+
+#define VINSX(SUFFIX, TYPE) \
+void glue(glue(helper_VINS, SUFFIX), LX)(CPUPPCState *env, ppc_avr_t *t, \
+ uint64_t val, target_ulong index) \
+{ \
+ const int maxidx = ARRAY_SIZE(t->u8) - sizeof(TYPE); \
+ target_long idx = index; \
+ \
+ if (idx < 0 || idx > maxidx) { \
+ idx = idx < 0 ? sizeof(TYPE) - idx : idx; \
+ qemu_log_mask(LOG_GUEST_ERROR, \
+ "Invalid index for Vector Insert Element after 0x" TARGET_FMT_lx \
+ ", RA = " TARGET_FMT_ld " > %d\n", env->nip, idx, maxidx); \
+ } else { \
+ TYPE src = val; \
+ memcpy(ELEM_ADDR(t, idx, sizeof(TYPE)), &src, sizeof(TYPE)); \
+ } \
+}
+VINSX(B, uint8_t)
+VINSX(H, uint16_t)
+VINSX(W, uint32_t)
+VINSX(D, uint64_t)
+#undef ELEM_ADDR
+#undef VINSX
#if defined(HOST_WORDS_BIGENDIAN)
#define VEXTRACT(suffix, element) \
void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6edffd5637..21af60c616 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1238,6 +1238,56 @@ GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
vinsertw, PPC_NONE, PPC2_ISA300);
+static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
+ TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ TCGv_ptr t;
+ TCGv idx;
+
+ t = gen_avr_ptr(vrt);
+ idx = tcg_temp_new();
+
+ tcg_gen_andi_tl(idx, ra, 0xF);
+ if (right) {
+ tcg_gen_subfi_tl(idx, 16 - size, idx);
+ }
+
+ gen_helper(cpu_env, t, rb, idx);
+
+ tcg_temp_free_ptr(t);
+ tcg_temp_free(idx);
+
+ return true;
+}
+
+static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ val = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
+
+ ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
+TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
+TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
+TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
+TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
+
+TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
+TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
+TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
+TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (31 preceding siblings ...)
2021-11-09 5:51 ` [PULL 32/54] target/ppc: Implement Vector Insert from GPR using GPR index insns David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns David Gibson
` (21 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsw: Vector Insert Word from GPR using immediate-specified index
vinsd: Vector Insert Doubleword from GPR using immediate-specified
index
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-7-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 6 +++++
target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b794424496..e1f76aac34 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -44,6 +44,9 @@
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+&VX_uim4 vrt uim vrb
+@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -353,5 +356,8 @@ VINSWRX 000100 ..... ..... ..... 01110001111 @VX
VINSDLX 000100 ..... ..... ..... 01011001111 @VX
VINSDRX 000100 ..... ..... ..... 01111001111 @VX
+VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
+VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 21af60c616..9642cfa037 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1278,6 +1278,40 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
return ok;
}
+static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->uim > (16 - size)) {
+ /*
+ * PowerISA v3.1 says that the resulting value is undefined in this
+ * case, so just log a guest error and leave VRT unchanged. The
+ * real hardware would do a partial insert, e.g. if VRT is zeroed and
+ * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
+ * VRT = 0x0000...00001234, but we don't bother to reproduce this
+ * behavior as software shouldn't rely on it.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
+ " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+ 16 - size);
+ return true;
+ }
+
+ val = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
+
+ ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
+ gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1288,6 +1322,9 @@ TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
+TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (32 preceding siblings ...)
2021-11-09 5:51 ` [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree David Gibson
` (20 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
vinsbvlx: Vector Insert Byte from VSR using GPR-specified Left-Index
vinshvlx: Vector Insert Halfword from VSR using GPR-specified
Left-Index
vinswvlx: Vector Insert Word from VSR using GPR-specified Left-Index
vinsbvrx: Vector Insert Byte from VSR using GPR-specified Right-Index
vinshvrx: Vector Insert Halfword from VSR using GPR-specified
Right-Index
vinswvrx: Vector Insert Word from VSR using GPR-specified Right-Index
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-8-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 7 +++++++
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e1f76aac34..de410abf7d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -359,5 +359,12 @@ VINSDRX 000100 ..... ..... ..... 01111001111 @VX
VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
+VINSBVLX 000100 ..... ..... ..... 00000001111 @VX
+VINSBVRX 000100 ..... ..... ..... 00100001111 @VX
+VINSHVLX 000100 ..... ..... ..... 00001001111 @VX
+VINSHVRX 000100 ..... ..... ..... 00101001111 @VX
+VINSWVLX 000100 ..... ..... ..... 00010001111 @VX
+VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
+
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 9642cfa037..46d6890242 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1260,6 +1260,20 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
return true;
}
+static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
+ int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ bool ok;
+ TCGv_i64 val;
+
+ val = tcg_temp_new_i64();
+ get_avr64(val, vrb, true);
+ ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
+
+ tcg_temp_free_i64(val);
+ return ok;
+}
+
static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
@@ -1278,6 +1292,16 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
return ok;
}
+static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
+ gen_helper);
+}
+
static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
@@ -1325,6 +1349,14 @@ TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
+TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
+TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
+TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
+
+TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
+TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
+TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (33 preceding siblings ...)
2021-11-09 5:51 ` [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns David Gibson
` (19 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-9-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 4 ----
target/ppc/insn32.decode | 5 +++++
target/ppc/int_helper.c | 21 -------------------
target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++---------
target/ppc/translate/vmx-ops.c.inc | 10 +++------
5 files changed, 30 insertions(+), 42 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 80f88ce78b..356495f392 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -224,10 +224,6 @@ DEF_HELPER_3(vextractub, void, avr, avr, i32)
DEF_HELPER_3(vextractuh, void, avr, avr, i32)
DEF_HELPER_3(vextractuw, void, avr, avr, i32)
DEF_HELPER_3(vextractd, void, avr, avr, i32)
-DEF_HELPER_3(vinsertb, void, avr, avr, i32)
-DEF_HELPER_3(vinserth, void, avr, avr, i32)
-DEF_HELPER_3(vinsertw, void, avr, avr, i32)
-DEF_HELPER_3(vinsertd, void, avr, avr, i32)
DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index de410abf7d..2eb7fb4e92 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -347,6 +347,11 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
+VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
+VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
+VINSERTD 000100 ..... - .... ..... 01111001101 @VX_uim4
+
VINSBLX 000100 ..... ..... ..... 01000001111 @VX
VINSBRX 000100 ..... ..... ..... 01100001111 @VX
VINSHLX 000100 ..... ..... ..... 01001001111 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 80b7f8814f..6f9479fd53 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1612,27 +1612,6 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#endif
}
-#if defined(HOST_WORDS_BIGENDIAN)
-#define VINSERT(suffix, element) \
- void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
- { \
- memmove(&r->u8[index], &b->u8[8 - sizeof(r->element[0])], \
- sizeof(r->element[0])); \
- }
-#else
-#define VINSERT(suffix, element) \
- void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
- { \
- uint32_t d = (16 - index) - sizeof(r->element[0]); \
- memmove(&r->u8[d], &b->u8[8], sizeof(r->element[0])); \
- }
-#endif
-VINSERT(b, u8)
-VINSERT(h, u16)
-VINSERT(w, u32)
-VINSERT(d, u64)
-#undef VINSERT
-
#if defined(HOST_WORDS_BIGENDIAN)
#define ELEM_ADDR(VEC, IDX, SIZE) (&(VEC)->u8[IDX])
#else
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 46d6890242..6fd18690df 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1217,10 +1217,6 @@ GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
-GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
-GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
-GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
-GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
@@ -1231,12 +1227,6 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
vextractuh, PPC_NONE, PPC2_ISA300);
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE,
- vinsertb, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE,
- vinserth, PPC_NONE, PPC2_ISA300);
-GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE,
- vinsertw, PPC_NONE, PPC2_ISA300);
static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
@@ -1336,6 +1326,23 @@ static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
return ok;
}
+static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->uim > (16 - size)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
+ " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
+ 16 - size);
+ return true;
+ }
+
+ return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
+ gen_helper);
+}
+
TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
@@ -1357,6 +1364,11 @@ TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
+TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
+TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
+TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
+TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
+
static void gen_vsldoi(DisasContext *ctx)
{
TCGv_ptr ra, rb, rd;
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index f3f4855111..25ee715b43 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -225,13 +225,9 @@ GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000,
GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000,
PPC_ALTIVEC),
GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000),
-GEN_VXFORM_DUAL_INV(vspltisb, vinsertb, 6, 12, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
- PPC_ALTIVEC),
-GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
+GEN_VXFORM(vspltisb, 6, 12),
+GEN_VXFORM(vspltish, 6, 13),
+GEN_VXFORM(vspltisw, 6, 14),
GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (34 preceding siblings ...)
2021-11-09 5:51 ` [PULL 35/54] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 37/54] target/ppc: Introduce REQUIRE_VSX macro David Gibson
` (18 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Matheus Ferst, David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vextdubvlx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Left-Index
vextduhvlx: Vector Extract Double Unsigned Halfword to VSR using
GPR-specified Left-Index
vextduwvlx: Vector Extract Double Unsigned Word to VSR using
GPR-specified Left-Index
vextddvlx: Vector Extract Double Doubleword to VSR using
GPR-specified Left-Index
vextdubvrx: Vector Extract Double Unsigned Byte to VSR using
GPR-specified Right-Index
vextduhvrx: Vector Extract Double Unsigned Halfword to VSR using
GPR-specified Right-Index
vextduwvrx: Vector Extract Double Unsigned Word to VSR using
GPR-specified Right-Index
vextddvrx: Vector Extract Double Doubleword to VSR using
GPR-specified Right-Index
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-10-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 4 +++
target/ppc/insn32.decode | 12 +++++++++
target/ppc/int_helper.c | 39 +++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.c.inc | 37 +++++++++++++++++++++++++++
4 files changed, 92 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 356495f392..7ff1d055c4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -334,6 +334,10 @@ DEF_HELPER_2(vextuwlx, tl, tl, avr)
DEF_HELPER_2(vextubrx, tl, tl, avr)
DEF_HELPER_2(vextuhrx, tl, tl, avr)
DEF_HELPER_2(vextuwrx, tl, tl, avr)
+DEF_HELPER_5(VEXTDUBVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUHVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDUWVLX, void, env, avr, avr, avr, tl)
+DEF_HELPER_5(VEXTDDVLX, void, env, avr, avr, avr, tl)
DEF_HELPER_2(vsbox, void, avr, avr)
DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2eb7fb4e92..e438177b32 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -38,6 +38,9 @@
%dx_d 6:s10 16:5 0:1
@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+&VA vrt vra vrb rc
+@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
+
&VN vrt vra vrb sh
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
@@ -347,6 +350,15 @@ VPEXTD 000100 ..... ..... ..... 10110001101 @VX
## Vector Permute and Formatting Instruction
+VEXTDUBVLX 000100 ..... ..... ..... ..... 011000 @VA
+VEXTDUBVRX 000100 ..... ..... ..... ..... 011001 @VA
+VEXTDUHVLX 000100 ..... ..... ..... ..... 011010 @VA
+VEXTDUHVRX 000100 ..... ..... ..... ..... 011011 @VA
+VEXTDUWVLX 000100 ..... ..... ..... ..... 011100 @VA
+VEXTDUWVRX 000100 ..... ..... ..... ..... 011101 @VA
+VEXTDDVLX 000100 ..... ..... ..... ..... 011110 @VA
+VEXTDDVRX 000100 ..... ..... ..... ..... 011111 @VA
+
VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 6f9479fd53..b7861776c2 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1642,6 +1642,45 @@ VINSX(D, uint64_t)
#undef ELEM_ADDR
#undef VINSX
#if defined(HOST_WORDS_BIGENDIAN)
+#define VEXTDVLX(NAME, SIZE) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ target_ulong index) \
+{ \
+ const target_long idx = index; \
+ ppc_avr_t tmp[2] = { *a, *b }; \
+ memset(t, 0, sizeof(*t)); \
+ if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \
+ memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2 - SIZE], (void *)tmp + idx, SIZE); \
+ } else { \
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for " #NAME " after 0x" \
+ TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", \
+ env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
+ } \
+}
+#else
+#define VEXTDVLX(NAME, SIZE) \
+void helper_##NAME(CPUPPCState *env, ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ target_ulong index) \
+{ \
+ const target_long idx = index; \
+ ppc_avr_t tmp[2] = { *b, *a }; \
+ memset(t, 0, sizeof(*t)); \
+ if (idx >= 0 && idx + SIZE <= sizeof(tmp)) { \
+ memcpy(&t->u8[ARRAY_SIZE(t->u8) / 2], \
+ (void *)tmp + sizeof(tmp) - SIZE - idx, SIZE); \
+ } else { \
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for " #NAME " after 0x" \
+ TARGET_FMT_lx ", RC = " TARGET_FMT_ld " > %d\n", \
+ env->nip, idx < 0 ? SIZE - idx : idx, 32 - SIZE); \
+ } \
+}
+#endif
+VEXTDVLX(VEXTDUBVLX, 1)
+VEXTDVLX(VEXTDUHVLX, 2)
+VEXTDVLX(VEXTDUWVLX, 4)
+VEXTDVLX(VEXTDDVLX, 8)
+#undef VEXTDVLX
+#if defined(HOST_WORDS_BIGENDIAN)
#define VEXTRACT(suffix, element) \
void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
{ \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6fd18690df..8eb8d3a067 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1228,6 +1228,43 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
+static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
+{
+ TCGv_ptr vrt, vra, vrb;
+ TCGv rc;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ vrt = gen_avr_ptr(a->vrt);
+ vra = gen_avr_ptr(a->vra);
+ vrb = gen_avr_ptr(a->vrb);
+ rc = tcg_temp_new();
+
+ tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
+ if (right) {
+ tcg_gen_subfi_tl(rc, 32 - size, rc);
+ }
+ gen_helper(cpu_env, vrt, vra, vrb, rc);
+
+ tcg_temp_free_ptr(vrt);
+ tcg_temp_free_ptr(vra);
+ tcg_temp_free_ptr(vrb);
+ tcg_temp_free(rc);
+ return true;
+}
+
+TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
+TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
+TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
+TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
+
+TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
+TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
+TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
+TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
+
static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
{
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 37/54] target/ppc: Introduce REQUIRE_VSX macro
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (35 preceding siblings ...)
2021-11-09 5:51 ` [PULL 36/54] target/ppc: Implement Vector Extract Double to VSR using GPR index insns David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr David Gibson
` (17 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Bruno Larsen (billionai), Matheus Ferst, David Gibson
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Introduce the macro to centralize checking if the VSX facility is
enabled and handle it correctly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-11-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index fc9d35a7a8..e88b613093 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7354,6 +7354,14 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#define REQUIRE_VSX(CTX) \
+ do { \
+ if (unlikely(!(CTX)->vsx_enabled)) { \
+ gen_exception((CTX), POWERPC_EXCP_VSXU); \
+ return true; \
+ } \
+ } while (0)
+
#define REQUIRE_FPU(ctx) \
do { \
if (unlikely(!(ctx)->fpu_enabled)) { \
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (36 preceding siblings ...)
2021-11-09 5:51 ` [PULL 37/54] target/ppc: Introduce REQUIRE_VSX macro David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree David Gibson
` (16 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Changes get_cpu_vsr to receive a new argument indicating whether the
high or low part of the register is being accessed. This change improves
consistency between the interfaces used to access Vector and VSX
registers and helps to handle endianness in some cases.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-12-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.c.inc | 317 +++++++++++++---------------
1 file changed, 146 insertions(+), 171 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 57a7f73bba..d923c6a090 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1,23 +1,13 @@
/*** VSX extension ***/
-static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
+static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true));
+ tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high));
}
-static inline void get_cpu_vsrl(TCGv_i64 dst, int n)
+static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high)
{
- tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false));
-}
-
-static inline void set_cpu_vsrh(int n, TCGv_i64 src)
-{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true));
-}
-
-static inline void set_cpu_vsrl(int n, TCGv_i64 src)
-{
- tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false));
+ tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high));
}
static inline TCGv_ptr gen_vsr_ptr(int reg)
@@ -41,7 +31,7 @@ static void gen_##name(DisasContext *ctx) \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
gen_qemu_##operation(ctx, t0, EA); \
- set_cpu_vsrh(xT(ctx->opcode), t0); \
+ set_cpu_vsr(xT(ctx->opcode), t0, true); \
/* NOTE: cpu_vsrl is undefined */ \
tcg_temp_free(EA); \
tcg_temp_free_i64(t0); \
@@ -67,10 +57,10 @@ static void gen_lxvd2x(DisasContext *ctx)
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_gen_addi_tl(EA, EA, 8);
gen_qemu_ld64_i64(ctx, t0, EA);
- set_cpu_vsrl(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, false);
tcg_temp_free(EA);
tcg_temp_free_i64(t0);
}
@@ -109,8 +99,8 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_gen_addi_tl(EA, EA, 8);
tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
}
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -233,8 +223,8 @@ static void gen_lxvh8x(DisasContext *ctx)
if (ctx->le_mode) {
gen_bswap16x8(xth, xtl, xth, xtl);
}
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -258,8 +248,8 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
tcg_gen_addi_tl(EA, EA, 8);
tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free(EA);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -301,16 +291,16 @@ static void gen_##name(DisasContext *ctx) \
} \
if (ctx->le_mode) { \
tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsrl(xt, xtl); \
+ set_cpu_vsr(xt, xtl, false); \
tcg_gen_addi_tl(EA, EA, 8); \
tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsrh(xt, xth); \
+ set_cpu_vsr(xt, xth, true); \
} else { \
tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsrh(xt, xth); \
+ set_cpu_vsr(xt, xth, true); \
tcg_gen_addi_tl(EA, EA, 8); \
tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsrl(xt, xtl); \
+ set_cpu_vsr(xt, xtl, false); \
} \
tcg_temp_free(EA); \
tcg_temp_free_i64(xth); \
@@ -347,8 +337,8 @@ static void gen_##name(DisasContext *ctx) \
} \
xth = tcg_temp_new_i64(); \
xtl = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, xt); \
- get_cpu_vsrl(xtl, xt); \
+ get_cpu_vsr(xth, xt, true); \
+ get_cpu_vsr(xtl, xt, false); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
if (indexed) { \
@@ -421,7 +411,7 @@ static void gen_##name(DisasContext *ctx) \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
gen_qemu_##operation(ctx, xth, EA); \
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); \
/* NOTE: cpu_vsrl is undefined */ \
tcg_temp_free(EA); \
tcg_temp_free_i64(xth); \
@@ -443,7 +433,7 @@ static void gen_##name(DisasContext *ctx) \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
- get_cpu_vsrh(t0, xS(ctx->opcode)); \
+ get_cpu_vsr(t0, xS(ctx->opcode), true); \
gen_qemu_##operation(ctx, t0, EA); \
tcg_temp_free(EA); \
tcg_temp_free_i64(t0); \
@@ -468,10 +458,10 @@ static void gen_stxvd2x(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
- get_cpu_vsrh(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), true);
gen_qemu_st64_i64(ctx, t0, EA);
tcg_gen_addi_tl(EA, EA, 8);
- get_cpu_vsrl(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), false);
gen_qemu_st64_i64(ctx, t0, EA);
tcg_temp_free(EA);
tcg_temp_free_i64(t0);
@@ -489,8 +479,8 @@ static void gen_stxvw4x(DisasContext *ctx)
}
xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
+ get_cpu_vsr(xsl, xS(ctx->opcode), false);
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -529,8 +519,8 @@ static void gen_stxvh8x(DisasContext *ctx)
}
xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
+ get_cpu_vsr(xsl, xS(ctx->opcode), false);
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -566,8 +556,8 @@ static void gen_stxvb16x(DisasContext *ctx)
}
xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
- get_cpu_vsrl(xsl, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
+ get_cpu_vsr(xsl, xS(ctx->opcode), false);
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -590,7 +580,7 @@ static void gen_##name(DisasContext *ctx) \
return; \
} \
xth = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \
+ get_cpu_vsr(xth, rD(ctx->opcode) + 32, true); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
@@ -618,7 +608,7 @@ static void gen_mfvsrwz(DisasContext *ctx)
}
TCGv_i64 tmp = tcg_temp_new_i64();
TCGv_i64 xsh = tcg_temp_new_i64();
- get_cpu_vsrh(xsh, xS(ctx->opcode));
+ get_cpu_vsr(xsh, xS(ctx->opcode), true);
tcg_gen_ext32u_i64(tmp, xsh);
tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp);
tcg_temp_free_i64(tmp);
@@ -642,7 +632,7 @@ static void gen_mtvsrwa(DisasContext *ctx)
TCGv_i64 xsh = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_ext32s_i64(xsh, tmp);
- set_cpu_vsrh(xT(ctx->opcode), xsh);
+ set_cpu_vsr(xT(ctx->opcode), xsh, true);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(xsh);
}
@@ -664,7 +654,7 @@ static void gen_mtvsrwz(DisasContext *ctx)
TCGv_i64 xsh = tcg_temp_new_i64();
tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_ext32u_i64(xsh, tmp);
- set_cpu_vsrh(xT(ctx->opcode), xsh);
+ set_cpu_vsr(xT(ctx->opcode), xsh, true);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(xsh);
}
@@ -685,7 +675,7 @@ static void gen_mfvsrd(DisasContext *ctx)
}
}
t0 = tcg_temp_new_i64();
- get_cpu_vsrh(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), true);
tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
tcg_temp_free_i64(t0);
}
@@ -706,7 +696,7 @@ static void gen_mtvsrd(DisasContext *ctx)
}
t0 = tcg_temp_new_i64();
tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_temp_free_i64(t0);
}
@@ -725,7 +715,7 @@ static void gen_mfvsrld(DisasContext *ctx)
}
}
t0 = tcg_temp_new_i64();
- get_cpu_vsrl(t0, xS(ctx->opcode));
+ get_cpu_vsr(t0, xS(ctx->opcode), false);
tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0);
tcg_temp_free_i64(t0);
}
@@ -751,10 +741,10 @@ static void gen_mtvsrdd(DisasContext *ctx)
} else {
tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
}
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]);
- set_cpu_vsrl(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, false);
tcg_temp_free_i64(t0);
}
@@ -776,8 +766,8 @@ static void gen_mtvsrws(DisasContext *ctx)
t0 = tcg_temp_new_i64();
tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rA(ctx->opcode)], 32, 32);
- set_cpu_vsrl(xT(ctx->opcode), t0);
- set_cpu_vsrh(xT(ctx->opcode), t0);
+ set_cpu_vsr(xT(ctx->opcode), t0, false);
+ set_cpu_vsr(xT(ctx->opcode), t0, true);
tcg_temp_free_i64(t0);
}
@@ -797,33 +787,25 @@ static void gen_xxpermdi(DisasContext *ctx)
if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
(xT(ctx->opcode) == xB(ctx->opcode)))) {
- if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsrh(xh, xA(ctx->opcode));
- } else {
- get_cpu_vsrl(xh, xA(ctx->opcode));
- }
- if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsrh(xl, xB(ctx->opcode));
- } else {
- get_cpu_vsrl(xl, xB(ctx->opcode));
- }
+ get_cpu_vsr(xh, xA(ctx->opcode), (DM(ctx->opcode) & 2) == 0);
+ get_cpu_vsr(xl, xB(ctx->opcode), (DM(ctx->opcode) & 1) == 0);
- set_cpu_vsrh(xT(ctx->opcode), xh);
- set_cpu_vsrl(xT(ctx->opcode), xl);
+ set_cpu_vsr(xT(ctx->opcode), xh, true);
+ set_cpu_vsr(xT(ctx->opcode), xl, false);
} else {
if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsrh(xh, xA(ctx->opcode));
- set_cpu_vsrh(xT(ctx->opcode), xh);
+ get_cpu_vsr(xh, xA(ctx->opcode), true);
+ set_cpu_vsr(xT(ctx->opcode), xh, true);
} else {
- get_cpu_vsrl(xh, xA(ctx->opcode));
- set_cpu_vsrh(xT(ctx->opcode), xh);
+ get_cpu_vsr(xh, xA(ctx->opcode), false);
+ set_cpu_vsr(xT(ctx->opcode), xh, true);
}
if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsrh(xl, xB(ctx->opcode));
- set_cpu_vsrl(xT(ctx->opcode), xl);
+ get_cpu_vsr(xl, xB(ctx->opcode), true);
+ set_cpu_vsr(xT(ctx->opcode), xl, false);
} else {
- get_cpu_vsrl(xl, xB(ctx->opcode));
- set_cpu_vsrl(xT(ctx->opcode), xl);
+ get_cpu_vsr(xl, xB(ctx->opcode), false);
+ set_cpu_vsr(xT(ctx->opcode), xl, false);
}
}
tcg_temp_free_i64(xh);
@@ -847,7 +829,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
} \
xb = tcg_temp_new_i64(); \
sgm = tcg_temp_new_i64(); \
- get_cpu_vsrh(xb, xB(ctx->opcode)); \
+ get_cpu_vsr(xb, xB(ctx->opcode), true); \
tcg_gen_movi_i64(sgm, sgn_mask); \
switch (op) { \
case OP_ABS: { \
@@ -864,7 +846,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
} \
case OP_CPSGN: { \
TCGv_i64 xa = tcg_temp_new_i64(); \
- get_cpu_vsrh(xa, xA(ctx->opcode)); \
+ get_cpu_vsr(xa, xA(ctx->opcode), true); \
tcg_gen_and_i64(xa, xa, sgm); \
tcg_gen_andc_i64(xb, xb, sgm); \
tcg_gen_or_i64(xb, xb, xa); \
@@ -872,7 +854,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
break; \
} \
} \
- set_cpu_vsrh(xT(ctx->opcode), xb); \
+ set_cpu_vsr(xT(ctx->opcode), xb, true); \
tcg_temp_free_i64(xb); \
tcg_temp_free_i64(sgm); \
}
@@ -898,8 +880,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
xbl = tcg_temp_new_i64(); \
sgm = tcg_temp_new_i64(); \
tmp = tcg_temp_new_i64(); \
- get_cpu_vsrh(xbh, xb); \
- get_cpu_vsrl(xbl, xb); \
+ get_cpu_vsr(xbh, xb, true); \
+ get_cpu_vsr(xbl, xb, false); \
tcg_gen_movi_i64(sgm, sgn_mask); \
switch (op) { \
case OP_ABS: \
@@ -914,15 +896,15 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_CPSGN: \
xah = tcg_temp_new_i64(); \
xa = rA(ctx->opcode) + 32; \
- get_cpu_vsrh(tmp, xa); \
+ get_cpu_vsr(tmp, xa, true); \
tcg_gen_and_i64(xah, tmp, sgm); \
tcg_gen_andc_i64(xbh, xbh, sgm); \
tcg_gen_or_i64(xbh, xbh, xah); \
tcg_temp_free_i64(xah); \
break; \
} \
- set_cpu_vsrh(xt, xbh); \
- set_cpu_vsrl(xt, xbl); \
+ set_cpu_vsr(xt, xbh, true); \
+ set_cpu_vsr(xt, xbl, false); \
tcg_temp_free_i64(xbl); \
tcg_temp_free_i64(xbh); \
tcg_temp_free_i64(sgm); \
@@ -945,8 +927,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
xbh = tcg_temp_new_i64(); \
xbl = tcg_temp_new_i64(); \
sgm = tcg_temp_new_i64(); \
- get_cpu_vsrh(xbh, xB(ctx->opcode)); \
- get_cpu_vsrl(xbl, xB(ctx->opcode)); \
+ get_cpu_vsr(xbh, xB(ctx->opcode), true); \
+ get_cpu_vsr(xbl, xB(ctx->opcode), false); \
tcg_gen_movi_i64(sgm, sgn_mask); \
switch (op) { \
case OP_ABS: { \
@@ -967,8 +949,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_CPSGN: { \
TCGv_i64 xah = tcg_temp_new_i64(); \
TCGv_i64 xal = tcg_temp_new_i64(); \
- get_cpu_vsrh(xah, xA(ctx->opcode)); \
- get_cpu_vsrl(xal, xA(ctx->opcode)); \
+ get_cpu_vsr(xah, xA(ctx->opcode), true); \
+ get_cpu_vsr(xal, xA(ctx->opcode), false); \
tcg_gen_and_i64(xah, xah, sgm); \
tcg_gen_and_i64(xal, xal, sgm); \
tcg_gen_andc_i64(xbh, xbh, sgm); \
@@ -980,8 +962,8 @@ static void glue(gen_, name)(DisasContext *ctx) \
break; \
} \
} \
- set_cpu_vsrh(xT(ctx->opcode), xbh); \
- set_cpu_vsrl(xT(ctx->opcode), xbl); \
+ set_cpu_vsr(xT(ctx->opcode), xbh, true); \
+ set_cpu_vsr(xT(ctx->opcode), xbl, false); \
tcg_temp_free_i64(xbh); \
tcg_temp_free_i64(xbl); \
tcg_temp_free_i64(sgm); \
@@ -1193,9 +1175,9 @@ static void gen_##name(DisasContext *ctx) \
} \
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
- get_cpu_vsrh(t0, xB(ctx->opcode)); \
+ get_cpu_vsr(t0, xB(ctx->opcode), true); \
gen_helper_##name(t1, cpu_env, t0); \
- set_cpu_vsrh(xT(ctx->opcode), t1); \
+ set_cpu_vsr(xT(ctx->opcode), t1, true); \
tcg_temp_free_i64(t0); \
tcg_temp_free_i64(t1); \
}
@@ -1390,13 +1372,13 @@ static void gen_xxbrd(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_bswap64_i64(xth, xbh);
tcg_gen_bswap64_i64(xtl, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1419,12 +1401,12 @@ static void gen_xxbrh(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
gen_bswap16x8(xth, xtl, xbh, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1448,15 +1430,15 @@ static void gen_xxbrq(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
t0 = tcg_temp_new_i64();
tcg_gen_bswap64_i64(t0, xbl);
tcg_gen_bswap64_i64(xtl, xbh);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_gen_mov_i64(xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1480,12 +1462,12 @@ static void gen_xxbrw(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
gen_bswap32x4(xth, xtl, xbh, xbl);
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1527,23 +1509,16 @@ static void glue(gen_, name)(DisasContext *ctx) \
b0 = tcg_temp_new_i64(); \
b1 = tcg_temp_new_i64(); \
tmp = tcg_temp_new_i64(); \
- if (high) { \
- get_cpu_vsrh(a0, xA(ctx->opcode)); \
- get_cpu_vsrh(a1, xA(ctx->opcode)); \
- get_cpu_vsrh(b0, xB(ctx->opcode)); \
- get_cpu_vsrh(b1, xB(ctx->opcode)); \
- } else { \
- get_cpu_vsrl(a0, xA(ctx->opcode)); \
- get_cpu_vsrl(a1, xA(ctx->opcode)); \
- get_cpu_vsrl(b0, xB(ctx->opcode)); \
- get_cpu_vsrl(b1, xB(ctx->opcode)); \
- } \
+ get_cpu_vsr(a0, xA(ctx->opcode), high); \
+ get_cpu_vsr(a1, xA(ctx->opcode), high); \
+ get_cpu_vsr(b0, xB(ctx->opcode), high); \
+ get_cpu_vsr(b1, xB(ctx->opcode), high); \
tcg_gen_shri_i64(a0, a0, 32); \
tcg_gen_shri_i64(b0, b0, 32); \
tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \
- set_cpu_vsrh(xT(ctx->opcode), tmp); \
+ set_cpu_vsr(xT(ctx->opcode), tmp, true); \
tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \
- set_cpu_vsrl(xT(ctx->opcode), tmp); \
+ set_cpu_vsr(xT(ctx->opcode), tmp, false); \
tcg_temp_free_i64(a0); \
tcg_temp_free_i64(a1); \
tcg_temp_free_i64(b0); \
@@ -1624,40 +1599,40 @@ static void gen_xxsldwi(DisasContext *ctx)
switch (SHW(ctx->opcode)) {
case 0: {
- get_cpu_vsrh(xth, xA(ctx->opcode));
- get_cpu_vsrl(xtl, xA(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), true);
+ get_cpu_vsr(xtl, xA(ctx->opcode), false);
break;
}
case 1: {
TCGv_i64 t0 = tcg_temp_new_i64();
- get_cpu_vsrh(xth, xA(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), true);
tcg_gen_shli_i64(xth, xth, 32);
- get_cpu_vsrl(t0, xA(ctx->opcode));
+ get_cpu_vsr(t0, xA(ctx->opcode), false);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xth, xth, t0);
- get_cpu_vsrl(xtl, xA(ctx->opcode));
+ get_cpu_vsr(xtl, xA(ctx->opcode), false);
tcg_gen_shli_i64(xtl, xtl, 32);
- get_cpu_vsrh(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), true);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xtl, xtl, t0);
tcg_temp_free_i64(t0);
break;
}
case 2: {
- get_cpu_vsrl(xth, xA(ctx->opcode));
- get_cpu_vsrh(xtl, xB(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), false);
+ get_cpu_vsr(xtl, xB(ctx->opcode), true);
break;
}
case 3: {
TCGv_i64 t0 = tcg_temp_new_i64();
- get_cpu_vsrl(xth, xA(ctx->opcode));
+ get_cpu_vsr(xth, xA(ctx->opcode), false);
tcg_gen_shli_i64(xth, xth, 32);
- get_cpu_vsrh(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), true);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xth, xth, t0);
- get_cpu_vsrh(xtl, xB(ctx->opcode));
+ get_cpu_vsr(xtl, xB(ctx->opcode), true);
tcg_gen_shli_i64(xtl, xtl, 32);
- get_cpu_vsrl(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), false);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_or_i64(xtl, xtl, t0);
tcg_temp_free_i64(t0);
@@ -1665,8 +1640,8 @@ static void gen_xxsldwi(DisasContext *ctx)
}
}
- set_cpu_vsrh(xT(ctx->opcode), xth);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1694,8 +1669,8 @@ static void gen_##name(DisasContext *ctx) \
*/ \
if (uimm > 15) { \
tcg_gen_movi_i64(t1, 0); \
- set_cpu_vsrh(xT(ctx->opcode), t1); \
- set_cpu_vsrl(xT(ctx->opcode), t1); \
+ set_cpu_vsr(xT(ctx->opcode), t1, true); \
+ set_cpu_vsr(xT(ctx->opcode), t1, false); \
return; \
} \
tcg_gen_movi_i32(t0, uimm); \
@@ -1719,7 +1694,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
return;
}
t0 = tcg_temp_new_i64();
- get_cpu_vsrh(t0, xB(ctx->opcode));
+ get_cpu_vsr(t0, xB(ctx->opcode), true);
tcg_gen_extract_i64(rt, t0, 52, 11);
tcg_temp_free_i64(t0);
}
@@ -1737,12 +1712,12 @@ static void gen_xsxexpqp(DisasContext *ctx)
xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+ get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
tcg_gen_extract_i64(xth, xbh, 48, 15);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
tcg_gen_movi_i64(xtl, 0);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
tcg_temp_free_i64(xbh);
tcg_temp_free_i64(xth);
@@ -1766,7 +1741,7 @@ static void gen_xsiexpdp(DisasContext *ctx)
tcg_gen_andi_i64(t0, rb, 0x7FF);
tcg_gen_shli_i64(t0, t0, 52);
tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
/* dword[1] is undefined */
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1789,19 +1764,19 @@ static void gen_xsiexpqp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xah = tcg_temp_new_i64();
xal = tcg_temp_new_i64();
- get_cpu_vsrh(xah, rA(ctx->opcode) + 32);
- get_cpu_vsrl(xal, rA(ctx->opcode) + 32);
+ get_cpu_vsr(xah, rA(ctx->opcode) + 32, true);
+ get_cpu_vsr(xal, rA(ctx->opcode) + 32, false);
xbh = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
+ get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
t0 = tcg_temp_new_i64();
tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF);
tcg_gen_andi_i64(t0, xbh, 0x7FFF);
tcg_gen_shli_i64(t0, t0, 48);
tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
tcg_gen_mov_i64(xtl, xal);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1826,12 +1801,12 @@ static void gen_xsxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
- get_cpu_vsrh(t1, xB(ctx->opcode));
+ get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- get_cpu_vsrh(t1, xB(ctx->opcode));
+ get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
tcg_temp_free_i64(t0);
@@ -1857,8 +1832,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, rB(ctx->opcode) + 32);
- get_cpu_vsrl(xbl, rB(ctx->opcode) + 32);
+ get_cpu_vsr(xbh, rB(ctx->opcode) + 32, true);
+ get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
@@ -1869,9 +1844,9 @@ static void gen_xsxsigqp(DisasContext *ctx)
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
- set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xth, true);
tcg_gen_mov_i64(xtl, xbl);
- set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
+ set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(exp);
@@ -1904,22 +1879,22 @@ static void gen_xviexpsp(DisasContext *ctx)
xal = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xah, xA(ctx->opcode));
- get_cpu_vsrl(xal, xA(ctx->opcode));
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xah, xA(ctx->opcode), true);
+ get_cpu_vsr(xal, xA(ctx->opcode), false);
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
t0 = tcg_temp_new_i64();
tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF);
tcg_gen_andi_i64(t0, xbh, 0xFF000000FF);
tcg_gen_shli_i64(t0, t0, 23);
tcg_gen_or_i64(xth, xth, t0);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF);
tcg_gen_andi_i64(t0, xbl, 0xFF000000FF);
tcg_gen_shli_i64(t0, t0, 23);
tcg_gen_or_i64(xtl, xtl, t0);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@ -1949,16 +1924,16 @@ static void gen_xviexpdp(DisasContext *ctx)
xal = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xah, xA(ctx->opcode));
- get_cpu_vsrl(xal, xA(ctx->opcode));
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xah, xA(ctx->opcode), true);
+ get_cpu_vsr(xal, xA(ctx->opcode), false);
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_deposit_i64(xth, xah, xbh, 52, 11);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -1983,15 +1958,15 @@ static void gen_xvxexpsp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_shri_i64(xth, xbh, 23);
tcg_gen_andi_i64(xth, xth, 0xFF000000FF);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_shri_i64(xtl, xbl, 23);
tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -2014,13 +1989,13 @@ static void gen_xvxexpdp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
tcg_gen_extract_i64(xth, xbh, 52, 11);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_extract_i64(xtl, xbl, 52, 11);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(xth);
tcg_temp_free_i64(xtl);
@@ -2046,8 +2021,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
xtl = tcg_temp_new_i64();
xbh = tcg_temp_new_i64();
xbl = tcg_temp_new_i64();
- get_cpu_vsrh(xbh, xB(ctx->opcode));
- get_cpu_vsrl(xbl, xB(ctx->opcode));
+ get_cpu_vsr(xbh, xB(ctx->opcode), true);
+ get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
@@ -2058,14 +2033,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
- set_cpu_vsrh(xT(ctx->opcode), xth);
+ set_cpu_vsr(xT(ctx->opcode), xth, true);
tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52);
- set_cpu_vsrl(xT(ctx->opcode), xtl);
+ set_cpu_vsr(xT(ctx->opcode), xtl, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(exp);
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (37 preceding siblings ...)
2021-11-09 5:51 ` [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 40/54] target/ppc: moved stxvx and lxvx " David Gibson
` (15 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Lucas Mateus Castro (alqotel), Richard Henderson, qemu-devel,
Luis Pires, qemu-ppc, Matheus Ferst, David Gibson
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved stxv and lxv implementation from the legacy system to
decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-13-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 8 +++++
target/ppc/translate.c | 17 ++--------
target/ppc/translate/vsx-impl.c.inc | 51 +++++++++++++++++++++++++++--
3 files changed, 59 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e438177b32..296d6d6c5a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -28,6 +28,9 @@
%dq_rtp 22:4 !function=times_2
@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
+%dq_rt_tsx 3:1 21:5
+@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -385,3 +388,8 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+
+# VSX Load/Store Instructions
+
+LXV 111101 ..... ..... ............ . 001 @DQ_TSX
+STXV 111101 ..... ..... ............ . 101 @DQ_TSX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e88b613093..9960df6e18 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7446,20 +7446,7 @@ static void gen_dform39(DisasContext *ctx)
/* handles stfdp, lxv, stxsd, stxssp lxvx */
static void gen_dform3D(DisasContext *ctx)
{
- if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
- switch (ctx->opcode & 0x7) {
- case 1: /* lxv */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_lxv(ctx);
- }
- break;
- case 5: /* stxv */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_stxv(ctx);
- }
- break;
- }
- } else { /* DS-FORM */
+ if ((ctx->opcode & 3) != 1) { /* DS-FORM */
switch (ctx->opcode & 0x3) {
case 0: /* stfdp */
if (ctx->insns_flags2 & PPC2_ISA205) {
@@ -7584,7 +7571,7 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
-/* handles stfdp, lxv, stxsd, stxssp, stxv */
+/* handles stfdp, stxsd, stxssp */
GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index d923c6a090..9da66b5348 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -307,7 +307,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_LOAD(lxv, ld_i64, 0)
VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
#define VSX_VECTOR_STORE(name, op, indexed) \
@@ -360,7 +359,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_STORE(stxv, st_i64, 0)
VSX_VECTOR_STORE(stxvx, st_i64, 1)
#ifdef TARGET_PPC64
@@ -2052,6 +2050,55 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_temp_free_i64(xbl);
}
+static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
+ int rt, bool store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+ MemOp mop;
+
+ xt = tcg_temp_new_i64();
+
+ mop = DEF_MEMOP(MO_Q);
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, ra, displ);
+
+ if (store) {
+ get_cpu_vsr(xt, rt, !ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ gen_addr_add(ctx, ea, ea, 8);
+ get_cpu_vsr(xt, rt, ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt, xt, !ctx->le_mode);
+ gen_addr_add(ctx, ea, ea, 8);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt, xt, ctx->le_mode);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+ return true;
+}
+
+static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+ if (a->rt >= 32) {
+ REQUIRE_VSX(ctx);
+ } else {
+ REQUIRE_VECTOR(ctx);
+ }
+
+ return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
+}
+
+TRANS(STXV, do_lstxv_D, true)
+TRANS(LXV, do_lstxv_D, false)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 40/54] target/ppc: moved stxvx and lxvx from legacy to decodtree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (38 preceding siblings ...)
2021-11-09 5:51 ` [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 41/54] target/ppc: added the instructions LXVP and STXVP David Gibson
` (14 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Lucas Mateus Castro (alqotel), Richard Henderson, qemu-devel,
qemu-ppc, Matheus Ferst, David Gibson
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved stxvx and lxvx implementation from the legacy system to
decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-14-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 5 ++
target/ppc/translate/vsx-impl.c.inc | 121 ++++------------------------
target/ppc/translate/vsx-ops.c.inc | 2 -
3 files changed, 20 insertions(+), 108 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 296d6d6c5a..3ce26b2e6e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -103,6 +103,9 @@
@X_tbp_s_rc ...... ....0 s:1 .... ....0 .......... rc:1 &X_tb_s_rc rt=%x_frtp rb=%x_frbp
+%x_rt_tsx 0:1 21:5
+@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
+
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -393,3 +396,5 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
+LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
+STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9da66b5348..1973bb18f3 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -255,112 +255,6 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_VECTOR_LOAD(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsr(xt, xtl, false); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- set_cpu_vsr(xt, xth, true); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsr(xt, xth, true); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- set_cpu_vsr(xt, xtl, false); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
-
-#define VSX_VECTOR_STORE(name, op, indexed) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- int xt; \
- TCGv EA; \
- TCGv_i64 xth; \
- TCGv_i64 xtl; \
- \
- if (indexed) { \
- xt = xT(ctx->opcode); \
- } else { \
- xt = DQxT(ctx->opcode); \
- } \
- \
- if (xt < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- xth = tcg_temp_new_i64(); \
- xtl = tcg_temp_new_i64(); \
- get_cpu_vsr(xth, xt, true); \
- get_cpu_vsr(xtl, xt, false); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (indexed) { \
- gen_addr_reg_index(ctx, EA); \
- } else { \
- gen_addr_imm_index(ctx, EA, 0x0F); \
- } \
- if (ctx->le_mode) { \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
- } else { \
- tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
- tcg_gen_addi_tl(EA, EA, 8); \
- tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
- } \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
- tcg_temp_free_i64(xtl); \
-}
-
-VSX_VECTOR_STORE(stxvx, st_i64, 1)
-
#ifdef TARGET_PPC64
#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
static void gen_##name(DisasContext *ctx) \
@@ -2096,8 +1990,23 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
}
+static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+ if (a->rt >= 32) {
+ REQUIRE_VSX(ctx);
+ } else {
+ REQUIRE_VECTOR(ctx);
+ }
+
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store);
+}
+
TRANS(STXV, do_lstxv_D, true)
TRANS(LXV, do_lstxv_D, false)
+TRANS(STXVX, do_lstxv_X, true)
+TRANS(LXVX, do_lstxv_X, false)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 1d41beef26..b94f3fa4e0 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -10,7 +10,6 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
@@ -25,7 +24,6 @@ GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 41/54] target/ppc: added the instructions LXVP and STXVP
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (39 preceding siblings ...)
2021-11-09 5:51 ` [PULL 40/54] target/ppc: moved stxvx and lxvx " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 42/54] target/ppc: added the instructions LXVPX and STXVPX David Gibson
` (13 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Lucas Mateus Castro (alqotel), Richard Henderson, qemu-devel,
Luis Pires, qemu-ppc, Matheus Ferst, David Gibson
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions lxvp and stxvp using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-15-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 5 +++
target/ppc/translate/vsx-impl.c.inc | 55 ++++++++++++++++++++++-------
2 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3ce26b2e6e..c252dec02f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -31,6 +31,9 @@
%dq_rt_tsx 3:1 21:5
@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
+%rt_tsxp 21:1 22:4 !function=times_2
+@DQ_TSXP ...... ..... ra:5 ............ .... &D si=%dq_si rt=%rt_tsxp
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -396,5 +399,7 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
+LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
+STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 1973bb18f3..05bf6ea40c 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1945,11 +1945,12 @@ static void gen_xvxsigdp(DisasContext *ctx)
}
static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
- int rt, bool store)
+ int rt, bool store, bool paired)
{
TCGv ea;
TCGv_i64 xt;
MemOp mop;
+ int rt1, rt2;
xt = tcg_temp_new_i64();
@@ -1958,18 +1959,42 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
gen_set_access_type(ctx, ACCESS_INT);
ea = do_ea_calc(ctx, ra, displ);
+ if (paired && ctx->le_mode) {
+ rt1 = rt + 1;
+ rt2 = rt;
+ } else {
+ rt1 = rt;
+ rt2 = rt + 1;
+ }
+
if (store) {
- get_cpu_vsr(xt, rt, !ctx->le_mode);
+ get_cpu_vsr(xt, rt1, !ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
gen_addr_add(ctx, ea, ea, 8);
- get_cpu_vsr(xt, rt, ctx->le_mode);
+ get_cpu_vsr(xt, rt1, ctx->le_mode);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ if (paired) {
+ gen_addr_add(ctx, ea, ea, 8);
+ get_cpu_vsr(xt, rt2, !ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ gen_addr_add(ctx, ea, ea, 8);
+ get_cpu_vsr(xt, rt2, ctx->le_mode);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ }
} else {
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
- set_cpu_vsr(rt, xt, !ctx->le_mode);
+ set_cpu_vsr(rt1, xt, !ctx->le_mode);
gen_addr_add(ctx, ea, ea, 8);
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
- set_cpu_vsr(rt, xt, ctx->le_mode);
+ set_cpu_vsr(rt1, xt, ctx->le_mode);
+ if (paired) {
+ gen_addr_add(ctx, ea, ea, 8);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt2, xt, !ctx->le_mode);
+ gen_addr_add(ctx, ea, ea, 8);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt2, xt, ctx->le_mode);
+ }
}
tcg_temp_free(ea);
@@ -1977,17 +2002,21 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
return true;
}
-static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
+static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
{
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ if (paired) {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ } else {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ }
- if (a->rt >= 32) {
+ if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
}
- return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store);
+ return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
@@ -2000,11 +2029,13 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
REQUIRE_VECTOR(ctx);
}
- return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store);
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, false);
}
-TRANS(STXV, do_lstxv_D, true)
-TRANS(LXV, do_lstxv_D, false)
+TRANS(STXV, do_lstxv_D, true, false)
+TRANS(LXV, do_lstxv_D, false, false)
+TRANS(STXVP, do_lstxv_D, true, true)
+TRANS(LXVP, do_lstxv_D, false, true)
TRANS(STXVX, do_lstxv_X, true)
TRANS(LXVX, do_lstxv_X, false)
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 42/54] target/ppc: added the instructions LXVPX and STXVPX
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (40 preceding siblings ...)
2021-11-09 5:51 ` [PULL 41/54] target/ppc: added the instructions LXVP and STXVP David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 43/54] target/ppc: added the instructions PLXV and PSTXV David Gibson
` (12 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Lucas Mateus Castro (alqotel), Richard Henderson, qemu-devel,
qemu-ppc, Matheus Ferst, David Gibson
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions lxvpx and stxvpx using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-16-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 3 +++
target/ppc/translate/vsx-impl.c.inc | 18 ++++++++++++------
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c252dec02f..e4508631b0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -108,6 +108,7 @@
%x_rt_tsx 0:1 21:5
@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
+@X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
&X_frtp_vrb frtp vrb
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
@@ -403,3 +404,5 @@ LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
+LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
+STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 05bf6ea40c..c66505ac71 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2019,25 +2019,31 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
-static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store)
+static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ if (paired) {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ } else {
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ }
- if (a->rt >= 32) {
+ if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
}
- return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, false);
+ return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
}
TRANS(STXV, do_lstxv_D, true, false)
TRANS(LXV, do_lstxv_D, false, false)
TRANS(STXVP, do_lstxv_D, true, true)
TRANS(LXVP, do_lstxv_D, false, true)
-TRANS(STXVX, do_lstxv_X, true)
-TRANS(LXVX, do_lstxv_X, false)
+TRANS(STXVX, do_lstxv_X, true, false)
+TRANS(LXVX, do_lstxv_X, false, false)
+TRANS(STXVPX, do_lstxv_X, true, true)
+TRANS(LXVPX, do_lstxv_X, false, true)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 43/54] target/ppc: added the instructions PLXV and PSTXV
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (41 preceding siblings ...)
2021-11-09 5:51 ` [PULL 42/54] target/ppc: added the instructions LXVPX and STXVPX David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 44/54] target/ppc: added the instructions PLXVP and PSTXVP David Gibson
` (11 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Lucas Mateus Castro (alqotel), Richard Henderson, qemu-devel,
qemu-ppc, Matheus Ferst, David Gibson
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions plxv and pstxv using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-17-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 10 ++++++++++
target/ppc/translate/vsx-impl.c.inc | 16 ++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 48756cd4ca..093439b370 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -23,6 +23,9 @@
@PLS_D ...... .. ... r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+@8LS_D_TSX ...... .. . .. r:1 .. .................. \
+ ..... rt:6 ra:5 ................ \
+ &PLS_D si=%pls_si
### Fixed-Point Load Instructions
@@ -137,3 +140,10 @@ PSTFD 000001 10 0--.-- .................. \
PNOP ................................ \
-------------------------------- @PNOP
}
+
+### VSX instructions
+
+PLXV 000001 00 0--.-- .................. \
+ 11001 ...... ..... ................ @8LS_D_TSX
+PSTXV 000001 00 0--.-- .................. \
+ 11011 ...... ..... ................ @8LS_D_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index c66505ac71..1972127a22 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2019,6 +2019,20 @@ static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
}
+static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
+ bool store, bool paired)
+{
+ arg_D d;
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_lstxv(ctx, d.ra, tcg_constant_tl(d.si), d.rt, store, paired);
+}
+
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
if (paired) {
@@ -2044,6 +2058,8 @@ TRANS(STXVX, do_lstxv_X, true, false)
TRANS(LXVX, do_lstxv_X, false, false)
TRANS(STXVPX, do_lstxv_X, true, true)
TRANS(LXVPX, do_lstxv_X, false, true)
+TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
+TRANS64(PLXV, do_lstxv_PLS_D, false, false)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 44/54] target/ppc: added the instructions PLXVP and PSTXVP
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (42 preceding siblings ...)
2021-11-09 5:51 ` [PULL 43/54] target/ppc: added the instructions PLXV and PSTXV David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 45/54] target/ppc: moved XXSPLTW to using decodetree David Gibson
` (10 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Lucas Mateus Castro (alqotel), Richard Henderson, qemu-devel,
qemu-ppc, Matheus Ferst, David Gibson
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Implemented the instructions plxvp and pstxvp using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-18-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 9 +++++++++
target/ppc/translate/vsx-impl.c.inc | 2 ++
2 files changed, 11 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 093439b370..880ac3edc7 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -27,6 +27,11 @@
..... rt:6 ra:5 ................ \
&PLS_D si=%pls_si
+%rt_tsxp 21:1 22:4 !function=times_2
+@8LS_D_TSXP ...... .. . .. r:1 .. .................. \
+ ...... ..... ra:5 ................ \
+ &PLS_D si=%pls_si rt=%rt_tsxp
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -147,3 +152,7 @@ PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
11011 ...... ..... ................ @8LS_D_TSX
+PLXVP 000001 00 0--.-- .................. \
+ 111010 ..... ..... ................ @8LS_D_TSXP
+PSTXVP 000001 00 0--.-- .................. \
+ 111110 ..... ..... ................ @8LS_D_TSXP
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 1972127a22..6c60e29cca 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2060,6 +2060,8 @@ TRANS(STXVPX, do_lstxv_X, true, true)
TRANS(LXVPX, do_lstxv_X, false, true)
TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
TRANS64(PLXV, do_lstxv_PLS_D, false, false)
+TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
+TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 45/54] target/ppc: moved XXSPLTW to using decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (43 preceding siblings ...)
2021-11-09 5:51 ` [PULL 44/54] target/ppc: added the instructions PLXVP and PSTXVP David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 46/54] target/ppc: moved XXSPLTIB " David Gibson
` (9 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, qemu-ppc, Bruno Larsen (billionai),
Matheus Ferst, David Gibson
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Changed the function that handles XXSPLTW emulation to using decodetree,
but still using the same logic.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-19-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 9 +++++++++
target/ppc/translate/vsx-impl.c.inc | 17 ++++++-----------
target/ppc/translate/vsx-ops.c.inc | 1 -
3 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e4508631b0..5d425ec076 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -116,6 +116,11 @@
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+&XX2 xt xb uim:uint8_t
+%xx2_xt 0:1 21:5
+%xx2_xb 1:1 11:5
+@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
+
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@@ -406,3 +411,7 @@ LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
+
+## VSX splat instruction
+
+XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 6c60e29cca..ce8796d139 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1436,26 +1436,21 @@ static void gen_xxsel(DisasContext *ctx)
vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
}
-static void gen_xxspltw(DisasContext *ctx)
+static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
{
- int rt = xT(ctx->opcode);
- int rb = xB(ctx->opcode);
- int uim = UIM(ctx->opcode);
int tofs, bofs;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
+ REQUIRE_VSX(ctx);
- tofs = vsr_full_offset(rt);
- bofs = vsr_full_offset(rb);
- bofs += uim << MO_32;
+ tofs = vsr_full_offset(a->xt);
+ bofs = vsr_full_offset(a->xb);
+ bofs += a->uim << MO_32;
#ifndef HOST_WORDS_BIG_ENDIAN
bofs ^= 8 | 4;
#endif
tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
+ return true;
}
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index b94f3fa4e0..b669b64d35 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
-GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 46/54] target/ppc: moved XXSPLTIB to using decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (44 preceding siblings ...)
2021-11-09 5:51 ` [PULL 45/54] target/ppc: moved XXSPLTW to using decodetree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 47/54] target/ppc: implemented XXSPLTI32DX David Gibson
` (8 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, qemu-ppc, Bruno Larsen (billionai),
Matheus Ferst, David Gibson
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Changed the function that handles XXSPLTIB emulation to using
decodetree, but still use the same logic as before
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-20-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 5 +++++
target/ppc/translate/vsx-impl.c.inc | 20 ++++++--------------
target/ppc/translate/vsx-ops.c.inc | 1 -
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 5d425ec076..fd73946122 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -96,6 +96,10 @@
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+%x_xt 0:1 21:5
+&X_imm8 xt imm:uint8_t
+@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+
&X_tb_sp_rc rt rb sp rc:bool
@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
@@ -414,4 +418,5 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
## VSX splat instruction
+XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index ce8796d139..ad25a0daf0 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1455,23 +1455,15 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
-static void gen_xxspltib(DisasContext *ctx)
+static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
{
- uint8_t uim8 = IMM8(ctx->opcode);
- int rt = xT(ctx->opcode);
-
- if (rt < 32) {
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
+ if (a->xt < 32) {
+ REQUIRE_VSX(ctx);
} else {
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
+ REQUIRE_VECTOR(ctx);
}
- tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
+ tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(a->xt), 16, 16, a->imm);
+ return true;
}
static void gen_xxsldwi(DisasContext *ctx)
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index b669b64d35..152d1e5c3b 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
-GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 47/54] target/ppc: implemented XXSPLTI32DX
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (45 preceding siblings ...)
2021-11-09 5:51 ` [PULL 46/54] target/ppc: moved XXSPLTIB " David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 48/54] target/ppc: Implemented XXSPLTIW using decodetree David Gibson
` (7 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, qemu-ppc, Bruno Larsen (billionai),
Matheus Ferst, David Gibson
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented XXSPLTI32DX emulation using decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-21-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 11 +++++++++++
target/ppc/translate/vsx-impl.c.inc | 17 +++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 880ac3edc7..134bc60c57 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,14 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
+# Format 8RR:D
+%8rr_si 32:s16 0:16
+%8rr_xt 16:1 21:5
+&8RR_D_IX xt ix si
+@8RR_D_IX ...... .. .... .. .. ................ \
+ ...... ..... ... ix:1 . ................ \
+ &8RR_D_IX si=%8rr_si xt=%8rr_xt
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -156,3 +164,6 @@ PLXVP 000001 00 0--.-- .................. \
111010 ..... ..... ................ @8LS_D_TSXP
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+
+XXSPLTI32DX 000001 01 0000 -- -- ................ \
+ 100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index ad25a0daf0..360593a9ab 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,23 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
return true;
}
+static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
+{
+ TCGv_i32 imm;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ imm = tcg_constant_i32(a->si);
+
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 48/54] target/ppc: Implemented XXSPLTIW using decodetree
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (46 preceding siblings ...)
2021-11-09 5:51 ` [PULL 47/54] target/ppc: implemented XXSPLTI32DX David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:51 ` [PULL 49/54] target/ppc: implemented XXSPLTIDP instruction David Gibson
` (6 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, qemu-ppc, Bruno Larsen (billionai),
Matheus Ferst, David Gibson
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented the XXSPLTIW instruction, using decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-22-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 6 ++++++
target/ppc/translate/vsx-impl.c.inc | 10 ++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 134bc60c57..bd71f616cc 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,10 @@
@8RR_D_IX ...... .. .... .. .. ................ \
...... ..... ... ix:1 . ................ \
&8RR_D_IX si=%8rr_si xt=%8rr_xt
+&8RR_D xt si:int32_t
+@8RR_D ...... .. .... .. .. ................ \
+ ...... ..... .... . ................ \
+ &8RR_D si=%8rr_si xt=%8rr_xt
### Fixed-Point Load Instructions
@@ -165,5 +169,7 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXSPLTIW 000001 01 0000 -- -- ................ \
+ 100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 360593a9ab..7116141a6a 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,16 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
return true;
}
+static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_dup_imm(MO_32, vsr_full_offset(a->xt), 16, 16, a->si);
+
+ return true;
+}
+
static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
{
TCGv_i32 imm;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 49/54] target/ppc: implemented XXSPLTIDP instruction
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (47 preceding siblings ...)
2021-11-09 5:51 ` [PULL 48/54] target/ppc: Implemented XXSPLTIW using decodetree David Gibson
@ 2021-11-09 5:51 ` David Gibson
2021-11-09 5:52 ` [PULL 50/54] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions David Gibson
` (5 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:51 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, qemu-ppc, Bruno Larsen (billionai),
Matheus Ferst, David Gibson
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented the instruction XXSPLTIDP using decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-23-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn64.decode | 2 ++
target/ppc/translate/vsx-impl.c.inc | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index bd71f616cc..20aa2b4615 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -169,6 +169,8 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXSPLTIDP 000001 01 0000 -- -- ................ \
+ 100000 ..... 0010 . ................ @8RR_D
XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 7116141a6a..180d329f1a 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1476,6 +1476,16 @@ static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
return true;
}
+static bool trans_XXSPLTIDP(DisasContext *ctx, arg_8RR_D *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_dup_imm(MO_64, vsr_full_offset(a->xt), 16, 16,
+ helper_todouble(a->si));
+ return true;
+}
+
static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
{
TCGv_i32 imm;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 50/54] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (48 preceding siblings ...)
2021-11-09 5:51 ` [PULL 49/54] target/ppc: implemented XXSPLTIDP instruction David Gibson
@ 2021-11-09 5:52 ` David Gibson
2021-11-09 5:52 ` [PULL 51/54] target/ppc: Implement lxvkq instruction David Gibson
` (4 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:52 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, qemu-ppc, Bruno Larsen,
Matheus Ferst, David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-24-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 4 +++
target/ppc/insn64.decode | 19 ++++++++++
target/ppc/int_helper.c | 15 ++++++++
target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++++++++++
4 files changed, 93 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7ff1d055c4..627811cefc 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -520,6 +520,10 @@ DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
+DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVH, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVW, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVD, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 20aa2b4615..39e610913d 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -44,6 +44,16 @@
...... ..... .... . ................ \
&8RR_D si=%8rr_si xt=%8rr_xt
+# Format XX4
+&XX4 xt xa xb xc
+%xx4_xt 0:1 21:5
+%xx4_xa 2:1 16:5
+%xx4_xb 1:1 11:5
+%xx4_xc 3:1 6:5
+@XX4 ........ ........ ........ ........ \
+ ...... ..... ..... ..... ..... .. .... \
+ &XX4 xt=%xx4_xt xa=%xx4_xa xb=%xx4_xb xc=%xx4_xc
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -175,3 +185,12 @@ XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
+
+XXBLENDVD 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 11 .... @XX4
+XXBLENDVW 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 10 .... @XX4
+XXBLENDVH 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 01 .... @XX4
+XXBLENDVB 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 00 .... @XX4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b7861776c2..9bc327bcba 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1737,6 +1737,21 @@ void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt,
*xt = t;
}
+#define XXBLEND(name, sz) \
+void glue(helper_XXBLENDV, name)(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ ppc_avr_t *c, uint32_t desc) \
+{ \
+ for (int i = 0; i < ARRAY_SIZE(t->glue(u, sz)); i++) { \
+ t->glue(u, sz)[i] = (c->glue(s, sz)[i] >> (sz - 1)) ? \
+ b->glue(u, sz)[i] : a->glue(u, sz)[i]; \
+ } \
+}
+XXBLEND(B, 8)
+XXBLEND(H, 16)
+XXBLEND(W, 32)
+XXBLEND(D, 64)
+#undef XXBLEND
+
#define VEXT_SIGNED(name, element, cast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 180d329f1a..d1de0da877 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2087,6 +2087,61 @@ TRANS64(PLXV, do_lstxv_PLS_D, false, false)
TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
+static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
+ TCGv_vec c)
+{
+ TCGv_vec tmp = tcg_temp_new_vec_matching(c);
+ tcg_gen_sari_vec(vece, tmp, c, (8 << vece) - 1);
+ tcg_gen_bitsel_vec(vece, t, tmp, b, a);
+ tcg_temp_free_vec(tmp);
+}
+
+static bool do_xxblendv(DisasContext *ctx, arg_XX4 *a, unsigned vece)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_sari_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVB,
+ .opt_opc = vecop_list,
+ .vece = MO_8
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVH,
+ .opt_opc = vecop_list,
+ .vece = MO_16
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVW,
+ .opt_opc = vecop_list,
+ .vece = MO_32
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVD,
+ .opt_opc = vecop_list,
+ .vece = MO_64
+ }
+ };
+
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_4(vsr_full_offset(a->xt), vsr_full_offset(a->xa),
+ vsr_full_offset(a->xb), vsr_full_offset(a->xc),
+ 16, 16, &ops[vece]);
+
+ return true;
+}
+
+TRANS(XXBLENDVB, do_xxblendv, MO_8)
+TRANS(XXBLENDVH, do_xxblendv, MO_16)
+TRANS(XXBLENDVW, do_xxblendv, MO_32)
+TRANS(XXBLENDVD, do_xxblendv, MO_64)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 51/54] target/ppc: Implement lxvkq instruction
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (49 preceding siblings ...)
2021-11-09 5:52 ` [PULL 50/54] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions David Gibson
@ 2021-11-09 5:52 ` David Gibson
2021-11-09 5:52 ` [PULL 52/54] target/ppc: cntlzdm/cnttzdm implementation without brcond David Gibson
` (3 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:52 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Richard Henderson, qemu-devel, Luis Pires, qemu-ppc,
Matheus Ferst, David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-25-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 7 +++++
target/ppc/translate/vsx-impl.c.inc | 43 +++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fd73946122..e135b8aba4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -100,6 +100,9 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+&X_uim5 xt uim:uint8_t
+@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
+
&X_tb_sp_rc rt rb sp rc:bool
@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
@@ -420,3 +423,7 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+
+## VSX Vector Load Special Value Instruction
+
+LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index d1de0da877..c0e38060b4 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1503,6 +1503,49 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
return true;
}
+static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
+{
+ static const uint64_t values[32] = {
+ 0, /* Unspecified */
+ 0x3FFF000000000000llu, /* QP +1.0 */
+ 0x4000000000000000llu, /* QP +2.0 */
+ 0x4000800000000000llu, /* QP +3.0 */
+ 0x4001000000000000llu, /* QP +4.0 */
+ 0x4001400000000000llu, /* QP +5.0 */
+ 0x4001800000000000llu, /* QP +6.0 */
+ 0x4001C00000000000llu, /* QP +7.0 */
+ 0x7FFF000000000000llu, /* QP +Inf */
+ 0x7FFF800000000000llu, /* QP dQNaN */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0, /* Unspecified */
+ 0x8000000000000000llu, /* QP -0.0 */
+ 0xBFFF000000000000llu, /* QP -1.0 */
+ 0xC000000000000000llu, /* QP -2.0 */
+ 0xC000800000000000llu, /* QP -3.0 */
+ 0xC001000000000000llu, /* QP -4.0 */
+ 0xC001400000000000llu, /* QP -5.0 */
+ 0xC001800000000000llu, /* QP -6.0 */
+ 0xC001C00000000000llu, /* QP -7.0 */
+ 0xFFFF000000000000llu, /* QP -Inf */
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (values[a->uim]) {
+ set_cpu_vsr(a->xt, tcg_constant_i64(0x0), false);
+ set_cpu_vsr(a->xt, tcg_constant_i64(values[a->uim]), true);
+ } else {
+ gen_invalid(ctx);
+ }
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 52/54] target/ppc: cntlzdm/cnttzdm implementation without brcond
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (50 preceding siblings ...)
2021-11-09 5:52 ` [PULL 51/54] target/ppc: Implement lxvkq instruction David Gibson
@ 2021-11-09 5:52 ` David Gibson
2021-11-09 5:52 ` [PULL 53/54] target/ppc, hw/ppc: Change maintainers David Gibson
` (2 subsequent siblings)
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:52 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: Matheus Ferst, Richard Henderson, qemu-ppc, qemu-devel,
David Gibson
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-26-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/fixedpoint-impl.c.inc | 31 +++++++++++-----------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index e093562e2a..7fecff4579 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -416,32 +416,33 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
{
- TCGv_i64 tmp;
- TCGLabel *l1;
+ TCGv_i64 t0, t1;
- tmp = tcg_temp_local_new_i64();
- l1 = gen_new_label();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
- tcg_gen_and_i64(tmp, src, mask);
+ tcg_gen_and_i64(t0, src, mask);
if (trail) {
- tcg_gen_ctzi_i64(tmp, tmp, 64);
+ tcg_gen_ctzi_i64(t0, t0, -1);
} else {
- tcg_gen_clzi_i64(tmp, tmp, 64);
+ tcg_gen_clzi_i64(t0, t0, -1);
}
- tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
-
- tcg_gen_subfi_i64(tmp, 64, tmp);
+ tcg_gen_setcondi_i64(TCG_COND_NE, t1, t0, -1);
+ tcg_gen_andi_i64(t0, t0, 63);
+ tcg_gen_xori_i64(t0, t0, 63);
if (trail) {
- tcg_gen_shl_i64(tmp, mask, tmp);
+ tcg_gen_shl_i64(t0, mask, t0);
+ tcg_gen_shl_i64(t0, t0, t1);
} else {
- tcg_gen_shr_i64(tmp, mask, tmp);
+ tcg_gen_shr_i64(t0, mask, t0);
+ tcg_gen_shr_i64(t0, t0, t1);
}
- tcg_gen_ctpop_i64(tmp, tmp);
- gen_set_label(l1);
+ tcg_gen_ctpop_i64(dst, t0);
- tcg_gen_mov_i64(dst, tmp);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
}
static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 53/54] target/ppc, hw/ppc: Change maintainers
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (51 preceding siblings ...)
2021-11-09 5:52 ` [PULL 52/54] target/ppc: cntlzdm/cnttzdm implementation without brcond David Gibson
@ 2021-11-09 5:52 ` David Gibson
2021-11-09 5:52 ` [PULL 54/54] spapr_numa.c: FORM2 table handle nodes with no distance info David Gibson
2021-11-09 8:41 ` [PULL 00/54] ppc-for-6.2 queue 20211109 Richard Henderson
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:52 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug; +Cc: qemu-ppc, qemu-devel, David Gibson
As our day jobs and interests have moved onto other things, Greg and I have
been struggling to keep on top of maintainership of target/ppc and
associated pieces like the pseries and powernv machine types, with their
platform specific devices.
We've therefore discussed and plan to transfer maintainership to Cédric Le
Goater (primary) and Daniel Henrique Barboza (backup). Cédric and Daniel
have been actively contributing to the area for some time, and they're
supported in this by their current employer, IBM, who has an obvious
interest in the platform.
Greg and I do plan to stay around in some capacity for at least the next
6 months, providing reviews and advice to assist the new maintainers into
the role.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Acked-by: Cédric Le Goater <clg@kaod.org>
---
MAINTAINERS | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 53b63df407..d3879aa3c1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -262,8 +262,10 @@ F: hw/openrisc/
F: tests/tcg/openrisc/
PowerPC TCG CPUs
-M: David Gibson <david@gibson.dropbear.id.au>
-M: Greg Kurz <groug@kaod.org>
+M: Cédric Le Goater <clg@kaod.org>
+M: Daniel Henrique Barboza <danielhb413@gmail.com>
+R: David Gibson <david@gibson.dropbear.id.au>
+R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
F: target/ppc/
@@ -382,8 +384,10 @@ F: target/mips/kvm*
F: target/mips/sysemu/
PPC KVM CPUs
-M: David Gibson <david@gibson.dropbear.id.au>
-M: Greg Kurz <groug@kaod.org>
+M: Cédric Le Goater <clg@kaod.org>
+M: Daniel Henrique Barboza <danielhb413@gmail.com>
+R: David Gibson <david@gibson.dropbear.id.au>
+R: Greg Kurz <groug@kaod.org>
S: Maintained
F: target/ppc/kvm.c
@@ -1321,8 +1325,10 @@ F: include/hw/rtc/m48t59.h
F: tests/avocado/ppc_prep_40p.py
sPAPR
-M: David Gibson <david@gibson.dropbear.id.au>
-M: Greg Kurz <groug@kaod.org>
+M: Cédric Le Goater <clg@kaod.org>
+M: Daniel Henrique Barboza <danielhb413@gmail.com>
+R: David Gibson <david@gibson.dropbear.id.au>
+R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
S: Maintained
F: hw/*/spapr*
@@ -1382,6 +1388,8 @@ F: include/hw/pci-host/mv64361.h
Virtual Open Firmware (VOF)
M: Alexey Kardashevskiy <aik@ozlabs.ru>
+R: Cédric Le Goater <clg@kaod.org>
+R: Daniel Henrique Barboza <danielhb413@gmail.com>
R: David Gibson <david@gibson.dropbear.id.au>
R: Greg Kurz <groug@kaod.org>
L: qemu-ppc@nongnu.org
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PULL 54/54] spapr_numa.c: FORM2 table handle nodes with no distance info
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (52 preceding siblings ...)
2021-11-09 5:52 ` [PULL 53/54] target/ppc, hw/ppc: Change maintainers David Gibson
@ 2021-11-09 5:52 ` David Gibson
2021-11-09 8:41 ` [PULL 00/54] ppc-for-6.2 queue 20211109 Richard Henderson
54 siblings, 0 replies; 60+ messages in thread
From: David Gibson @ 2021-11-09 5:52 UTC (permalink / raw)
To: peter.maydell, clg, danielhb413, groug
Cc: qemu-ppc, qemu-devel, Nicholas Piggin, David Gibson
From: Nicholas Piggin <npiggin@gmail.com>
A configuration that specifies multiple nodes without distance info
results in the non-local points in the FORM2 matrix having a distance of
0. This causes Linux to complain "Invalid distance value range" because
a node distance is smaller than the local distance.
Fix this by building a simple local / remote fallback for points where
distance information is missing.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20211105135137.1584840-1-npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_numa.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_numa.c b/hw/ppc/spapr_numa.c
index 5822938448..56ab2a5fb6 100644
--- a/hw/ppc/spapr_numa.c
+++ b/hw/ppc/spapr_numa.c
@@ -546,12 +546,24 @@ static void spapr_numa_FORM2_write_rtas_tables(SpaprMachineState *spapr,
* NUMA nodes, but QEMU adds the default NUMA node without
* adding the numa_info to retrieve distance info from.
*/
- if (src == dst) {
- distance_table[i++] = NUMA_DISTANCE_MIN;
- continue;
+ distance_table[i] = numa_info[src].distance[dst];
+ if (distance_table[i] == 0) {
+ /*
+ * In case QEMU adds a default NUMA single node when the user
+ * did not add any, or where the user did not supply distances,
+ * the value will be 0 here. Populate the table with a fallback
+ * simple local / remote distance.
+ */
+ if (src == dst) {
+ distance_table[i] = NUMA_DISTANCE_MIN;
+ } else {
+ distance_table[i] = numa_info[src].distance[dst];
+ if (distance_table[i] < NUMA_DISTANCE_MIN) {
+ distance_table[i] = NUMA_DISTANCE_DEFAULT;
+ }
+ }
}
-
- distance_table[i++] = numa_info[src].distance[dst];
+ i++;
}
}
--
2.33.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PULL 00/54] ppc-for-6.2 queue 20211109
2021-11-09 5:51 [PULL 00/54] ppc-for-6.2 queue 20211109 David Gibson
` (53 preceding siblings ...)
2021-11-09 5:52 ` [PULL 54/54] spapr_numa.c: FORM2 table handle nodes with no distance info David Gibson
@ 2021-11-09 8:41 ` Richard Henderson
54 siblings, 0 replies; 60+ messages in thread
From: Richard Henderson @ 2021-11-09 8:41 UTC (permalink / raw)
To: David Gibson, peter.maydell, clg, danielhb413, groug; +Cc: qemu-ppc, qemu-devel
On 11/9/21 6:51 AM, David Gibson wrote:
> The following changes since commit 114f3c8cc427333dbae331dfd2ecae64676b087e:
>
> Merge remote-tracking branch 'remotes/philmd/tags/avocado-20211108' into staging (2021-11-08 18:50:09 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.2-20211109
>
> for you to fetch changes up to 71e6fae3a994ab5c69e37d6a52a30c840883fbfb:
>
> spapr_numa.c: FORM2 table handle nodes with no distance info (2021-11-09 10:32:53 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue for 2021-11-09
>
> Here's the latest set of ppc related patches for qemu-6.2, which I
> hope will squeeze in just barely before the hard freeze.
>
> This set includes a change to MAINTAINERS moving maintainership of ppc
> from myself and Greg Kurz to Cédric le Goater and Daniel Henrique
> Barboza. So, I expect this to be my last pull request as ppc
> maintainer. It's been great, but it's time I moved onto other things.
>
> Apart from that, this patchset is mostly a lot of updates to TCG
> implementations of ISA 3.1 (POWER10) instructions from the El Dorado
> team. There are also a handful of other fixes.
>
> ----------------------------------------------------------------
> BALATON Zoltan (1):
> ppc/pegasos2: Suppress warning when qtest enabled
>
> Bruno Larsen (1):
> target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c
>
> Bruno Larsen (billionai) (6):
> target/ppc: Introduce REQUIRE_VSX macro
> target/ppc: moved XXSPLTW to using decodetree
> target/ppc: moved XXSPLTIB to using decodetree
> target/ppc: implemented XXSPLTI32DX
> target/ppc: Implemented XXSPLTIW using decodetree
> target/ppc: implemented XXSPLTIDP instruction
>
> Cédric Le Goater (1):
> ppc/pnv: Fix check on block device before updating drive contents
>
> David Gibson (1):
> target/ppc, hw/ppc: Change maintainers
>
> Fernando Eckhardt Valle (4):
> target/ppc: introduce do_ea_calc
> target/ppc: move resolve_PLS_D to translate.c
> target/ppc: Move load and store floating point instructions to decodetree
> target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions
>
> Fernando Valle (1):
> target/ppc: Introduce REQUIRE_FPU
>
> Lucas Mateus Castro (alqotel) (6):
> target/ppc: moved stxv and lxv from legacy to decodtree
> target/ppc: moved stxvx and lxvx from legacy to decodtree
> target/ppc: added the instructions LXVP and STXVP
> target/ppc: added the instructions LXVPX and STXVPX
> target/ppc: added the instructions PLXV and PSTXV
> target/ppc: added the instructions PLXVP and PSTXVP
>
> Luis Pires (15):
> target/ppc: Implement cntlzdm
> target/ppc: Implement cnttzdm
> libdecnumber: introduce decNumberFrom[U]Int128
> target/ppc: Implement DCFFIXQQ
> host-utils: Introduce mulu128
> libdecnumber: Introduce decNumberIntegralToInt128
> target/ppc: Implement DCTFIXQQ
> target/ppc: Do not update nip on DFP instructions
> target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree
> target/ppc: Move d{add,sub,mul,div,iex}[q] to decodetree
> target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree
> target/ppc: Move dquai[q], drint{x,n}[q] to decodetree
> target/ppc: Move dqua[q], drrnd[q] to decodetree
> target/ppc: Move dct{dp,qpq},dr{sp,dpq},dc{f,t}fix[q],dxex[q] to decodetree
> target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree
>
> Matheus Ferst (17):
> target/ppc: Move LQ and STQ to decodetree
> target/ppc: Implement PLQ and PSTQ
> target/ppc: Implement pdepd instruction
> target/ppc: Implement pextd instruction
> target/ppc: Move vcfuged to vmx-impl.c.inc
> target/ppc: Implement vclzdm/vctzdm instructions
> target/ppc: Implement vpdepd/vpextd instruction
> target/ppc: Implement vsldbi/vsrdbi instructions
> target/ppc: Implement Vector Insert from GPR using GPR index insns
> target/ppc: Implement Vector Insert Word from GPR using Immediate insns
> target/ppc: Implement Vector Insert from VSR using GPR index insns
> target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree
> target/ppc: Implement Vector Extract Double to VSR using GPR index insns
> target/ppc: receive high/low as argument in get/set_cpu_vsr
> target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions
> target/ppc: Implement lxvkq instruction
> target/ppc: cntlzdm/cnttzdm implementation without brcond
>
> Nicholas Piggin (1):
> spapr_numa.c: FORM2 table handle nodes with no distance info
>
> MAINTAINERS | 20 +-
> hw/ppc/pegasos2.c | 3 +-
> hw/ppc/pnv_pnor.c | 2 +-
> hw/ppc/spapr_numa.c | 22 +-
> include/libdecnumber/decNumber.h | 4 +
> include/libdecnumber/decNumberLocal.h | 2 +-
> include/qemu/host-utils.h | 36 ++
> libdecnumber/decContext.c | 7 +-
> libdecnumber/decNumber.c | 131 ++++++
> target/ppc/dfp_helper.c | 168 ++++---
> target/ppc/helper.h | 126 +++---
> target/ppc/insn32.decode | 303 +++++++++++++
> target/ppc/insn64.decode | 72 +++
> target/ppc/int_helper.c | 135 +++++-
> target/ppc/translate.c | 238 +++-------
> target/ppc/translate/dfp-impl.c.inc | 419 +++++++++--------
> target/ppc/translate/dfp-ops.c.inc | 165 -------
> target/ppc/translate/fixedpoint-impl.c.inc | 219 +++++++--
> target/ppc/translate/fp-impl.c.inc | 261 ++++-------
> target/ppc/translate/fp-ops.c.inc | 29 --
> target/ppc/translate/vector-impl.c.inc | 56 ---
> target/ppc/translate/vmx-impl.c.inc | 334 +++++++++++++-
> target/ppc/translate/vmx-ops.c.inc | 10 +-
> target/ppc/translate/vsx-impl.c.inc | 702 +++++++++++++++++------------
> target/ppc/translate/vsx-ops.c.inc | 4 -
> 25 files changed, 2171 insertions(+), 1297 deletions(-)
> delete mode 100644 target/ppc/translate/dfp-ops.c.inc
> delete mode 100644 target/ppc/translate/vector-impl.c.inc
Applied, thanks.
Don't forget to update the changelog on the wiki for the new features.
r~
^ permalink raw reply [flat|nested] 60+ messages in thread