From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 00/14] Support UXL filed in xstatus
Date: Wed, 10 Nov 2021 15:04:38 +0800 [thread overview]
Message-ID: <20211110070452.48539-1-zhiwei_liu@c-sky.com> (raw)
In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
v2:
Split out vill from vtype
Remove context switch when xlen changes at exception
Use XL instead of OL in many places
Use pointer masking and XLEN for vector address
Define an common fuction to calculate address for ldst
LIU Zhiwei (14):
target/riscv: Sign extend pc for different XLEN
target/riscv: Ignore the pc bits above XLEN
target/riscv: Extend pc for runtime pc write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Calculate address according to XLEN
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Ajdust vector atomic check with XLEN
target/riscv: Fix check range for first fault only
target/riscv: Relax debug check for pm write
target/riscv: Adjust vector address with mask
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Split out the vill from vtype
target/riscv: Don't save pc when exception return
target/riscv: Enable uxl field write
target/riscv/cpu.c | 23 +++++-
target/riscv/cpu.h | 9 +++
target/riscv/cpu_helper.c | 47 +++++++++++-
target/riscv/csr.c | 42 ++++++++++-
target/riscv/gdbstub.c | 73 ++++++++++++++-----
target/riscv/helper.h | 6 +-
.../riscv/insn_trans/trans_privileged.c.inc | 7 +-
target/riscv/insn_trans/trans_rvd.c.inc | 23 +-----
target/riscv/insn_trans/trans_rvf.c.inc | 23 +-----
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-----
target/riscv/insn_trans/trans_rvv.c.inc | 12 +--
target/riscv/internals.h | 1 +
target/riscv/machine.c | 11 +++
target/riscv/op_helper.c | 7 +-
target/riscv/translate.c | 29 +++++++-
target/riscv/vector_helper.c | 54 +++++++++-----
16 files changed, 263 insertions(+), 126 deletions(-)
--
2.25.1
next reply other threads:[~2021-11-10 7:05 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 7:04 LIU Zhiwei [this message]
2021-11-10 7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10 9:42 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-10 10:52 ` Richard Henderson
2021-11-10 13:44 ` LIU Zhiwei
2021-11-10 14:40 ` Richard Henderson
2021-11-11 5:04 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11 ` Richard Henderson
2021-11-10 14:08 ` LIU Zhiwei
2021-11-10 14:43 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23 ` Richard Henderson
2021-11-10 14:26 ` LIU Zhiwei
2021-11-10 15:01 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-10 11:25 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27 ` Richard Henderson
2021-11-10 14:38 ` LIU Zhiwei
2021-11-10 15:02 ` Richard Henderson
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