qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
	bin.meng@windriver.com, Alistair.Francis@wdc.com,
	LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN
Date: Wed, 10 Nov 2021 15:04:43 +0800	[thread overview]
Message-ID: <20211110070452.48539-6-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/insn_trans/trans_rvd.c.inc | 23 ++---------------------
 target/riscv/insn_trans/trans_rvf.c.inc | 23 ++---------------------
 target/riscv/insn_trans/trans_rvi.c.inc | 18 ++----------------
 target/riscv/translate.c                | 13 +++++++++++++
 4 files changed, 19 insertions(+), 58 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 64fb0046f7..29066a8ef3 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -20,19 +20,10 @@
 
 static bool trans_fld(DisasContext *ctx, arg_fld *a)
 {
-    TCGv addr;
-
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
 
     mark_fs_dirty(ctx);
@@ -41,21 +32,11 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
 
 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
 {
-    TCGv addr;
-
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
-
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index b5459249c4..a33897db7d 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -26,19 +26,10 @@
 static bool trans_flw(DisasContext *ctx, arg_flw *a)
 {
     TCGv_i64 dest;
-    TCGv addr;
-
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     dest = cpu_fpr[a->rd];
     tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
     gen_nanbox_s(dest, dest);
@@ -49,21 +40,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
 
 static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
 {
-    TCGv addr;
-
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    addr = get_gpr(ctx, a->rs1, EXT_NONE);
-    if (a->imm) {
-        TCGv temp = tcg_temp_new();
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
-
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index e51dbc41c5..7a0b037594 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -137,14 +137,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
     TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
 
     tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
     gen_set_gpr(ctx, a->rd, dest);
@@ -178,16 +171,9 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
 
 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
 {
-    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv addr = get_address(ctx, a->rs1, a->imm);
     TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    if (a->imm) {
-        TCGv temp = temp_new(ctx);
-        tcg_gen_addi_tl(temp, addr, a->imm);
-        addr = temp;
-    }
-    addr = gen_pm_adjust_address(ctx, addr);
-
     tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     return true;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a6a73ced9e..f52f6ef246 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -303,6 +303,19 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
     }
 }
 
+static TCGv get_address(DisasContext *ctx, int rs1, int imm)
+{
+    TCGv addr = temp_new(ctx);
+    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+    tcg_gen_addi_tl(addr, src1, imm);
+    addr = gen_pm_adjust_address(ctx, addr);
+    if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32u_tl(addr, addr);
+    }
+    return addr;
+}
+
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
-- 
2.25.1



  parent reply	other threads:[~2021-11-10  7:08 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-10  7:04 [PATCH v2 00/14] Support UXL filed in xstatus LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10  9:42   ` LIU Zhiwei
2021-11-10  7:04 ` LIU Zhiwei [this message]
2021-11-10 10:52   ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN Richard Henderson
2021-11-10 13:44     ` LIU Zhiwei
2021-11-10 14:40       ` Richard Henderson
2021-11-11  5:04         ` LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11   ` Richard Henderson
2021-11-10 14:08     ` LIU Zhiwei
2021-11-10 14:43       ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23   ` Richard Henderson
2021-11-10 14:26     ` LIU Zhiwei
2021-11-10 15:01       ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-10 11:25   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27   ` Richard Henderson
2021-11-10 14:38     ` LIU Zhiwei
2021-11-10 15:02       ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211110070452.48539-6-zhiwei_liu@c-sky.com \
    --to=zhiwei_liu@c-sky.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).