From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN
Date: Thu, 11 Nov 2021 13:57:43 +0800 [thread overview]
Message-ID: <20211111055800.42672-4-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211111055800.42672-1-zhiwei_liu@c-sky.com>
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9eeed38c7e..4c048cc266 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags = 0;
+ RISCVMXL xl = cpu_get_xl(env);
- *pc = env->pc;
+ *pc = xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
@@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#endif
- flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
*pflags = flags;
}
--
2.25.1
next prev parent reply other threads:[~2021-11-11 6:05 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 5:57 [PATCH v3 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei [this message]
2021-11-11 5:57 ` [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-11 11:19 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-11 11:21 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-11 11:26 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-11 11:28 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-11 11:29 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-11 11:31 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-11 11:35 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-11 11:38 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 11:46 ` Richard Henderson
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 5:58 ` [PATCH v3 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 11:49 ` Richard Henderson
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 18:20 ` Richard Henderson
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